To all,
I'm generating an SOPC design in Quartus using the builder and have created a custom master, slave and used a sdram controller. The VHDL file that gets generated is a bit confusing to me, as it contains all the arbitration logic associated in interconnecting everything together; however, there are area's in the file that show up as "insert code here", and I'm not sure if this is the testbench file, or the behavioural file that represents the sopc design? I'm starting to develop my own test bench to connect the sopc design to an external memory model i got from a vendor. I'm curious to know whether I have to do this, or if the file that was geneated from SOPC buidler represents the test bench. The documentation on the files generated on the Altera website are still a bit vague on exactly what to do and how to do it.
Cheers, Pino