Altera SDRAM controller - Only 2 words burst???

Hi All,

I am trying to use the SDR SDRAM controller that is comming with the NIOS II development package. In the simulation it looks like this core supports only 2 words bursts. I couldn't find anything in the documentations. Am I correct? If this core supports bigger bursts then 2 words, any ideas what am I doing wrong?

Thank you all Zohar

Reply to
zg
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Zohar,

I'm working on a design that uses one 16MB sdram chip for most of its instruction and data memory. I rely heavily on dma and other burst reads and writes (ie cache) to get the performance I need.

The sdram controller you're talking about is good enough to burst 480 32 bit words in under 485 cpu clocks. It's a beautiful thing to watch in Signal Tap as I get this performance. (Haven't explored the lenght limits above

480 - my external fifo's AlmostFull level)

I'm hammering that sdram (through the Altera sdram controller) nines ways to Sunday and it performs flawlessly.

I have some serious issues with the whole NiosI/II chain, but the sdram controller has been a champ.

Ken

Reply to
Kenneth Land

Hi Ken,

Thank you for your response. What frequncy are you running the NIOS? I tried simulating at 72MHz and I got only 2 words bursts. Are you using NIOS II?

Regards, Zohar

Reply to
zg

Hi Zohar,

My system is running at 75 MHz right now. My fmax is 90+ so I may try a little higher too. I didn't simulate, but I used SignalTapII to verify that I was indeed dma'ing the contents of an external fifo into sdram at a rate of 1 clock per

32bit word. (480 words in ~485 cpu clocks) This was while my system was running out of the same sdram and operating on other sdram data simultaneously - so very good results!

I'd like to add that I got these perfect results with the help of the Altera Nios team. I'll be posting this setup on the IP section of the Nios Forum.

This was *writing* to sdram, and I haven't really looked at reads yet. Hopefully I'll be just as pleased with those results. In my case reads are not quite as critical as writes, as the data streaming in is real time and waits for no one.

Ken

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Reply to
Kenneth Land

Hi,

I expected that you can initialize the burst lenght after SDRAM startup. I just wonder what happens in case you have a nios-II cache miss. However I will have to spend some time simulating the whole bunch ...

Configuration of SDRAM burst length is a normal step in using SDRAM's, isn't it?

Best Regards Markus

Reply to
Markus Meng

Hi,

No config that I'm aware of other than in the SOPC builder wizard. I looked in the .ptf file and didn't see any additional settings that looked interesting.

Ken

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Reply to
Kenneth Land

Hi Kemmeth,

Thank you again for your help. What is the part number of the SDRAM chip you are using. Maybe the difference is that I am simulating a different (Maybe slower) chip.

Zohar

Reply to
zg

It is nice to hear of some progress using the Altera SDRAM controller. However, I must say I have not been so fortunate. I have been trying for some time to develop my own Master peripheral in SOPC builder to allow reads and writes to the SDRAM on my evaluation board. However, there isn't any proper documentation on how to do so. The NIOS makes a perfect master, but I do not want the overhead cost of a processor in my application. Just can't afford it. If anyone has an example of using SignalTap and more specifically viewing the interface of the Avalon Bus, that would help me tremendously in debugging the interface.

Pino

Reply to
Pino

Hi Zohar,

It's a single 32 bit Micron MT48LC4M32B2 just like the Cyclone devkit board.

Ken

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Reply to
Kenneth Land

Hi Pino,

It has been a long hard battle getting my ADC data streamed into my Nios for processing. I've been at it since May of this year and I've just now achieved success.

I've gone through streaming dma, master port, and several interrupt driven input fifo setups. Our problem was 99% correct data on day one, but still

99% correct data month(s) later. (only 100% is acceptable)

It was not until Altera found mercy on me and assisted me with this last 1%. I got them involved, because I thought I had found an actual bug in the dma controller. To their credit they took my evidence seriously.

I've had a couple local HW engineers along the way have to give up.

Altera demonstrated that it can work. I'd like to see more sample implementations, so that everyone can get the performance they need out of their designs quickly.

SOPC and Nios are so incredible in power and ease of use, but it needs continuous improvement to "can" more and more cababilities.

Ken

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Reply to
Kenneth Land

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