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Altera Quartus FSM Simulation Delay?

To all,

I am currently using an example from a book which codes a simple FSM. The code is seen below. I simulate the following FSM obtained from a text book under Quartus 4.0 with the condition that "in1" signal is low for one clock-cycle commencing at the negative edge of the clock for an entire period. During this time, the state machine is in the "START" state, and the output changes to sequence = "continue" and the output changes immediately given a small delay (less than 1/2 clock period). I have sketched out the timing diagram as it appears in the simulation from the text book. For some reason, when I simulate this same state machine in Quartus with the same 10 ns clock period, I end up getting "out1" delayed by more than half the clock period. I'm simulating using a stratix chipset speed grade -6. Unbelievably long time of a propagation delay, so does this sound right to anyone?

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Reply to
Pino
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Hi,

It looks like out1 is a top-level output of your design. That means it is being implemented in an IO pad, and the delay you are getting includes the output pad delay driving the default load (10 pF for Stratix LVTTL IOs). That will be a significant delay. Also, there is a significant delay in getting the clock from the clock input pad (where the simulator monitors it) to the clock input of the various flip flops (unless you use a PLL).

So a ~5 ns delay (Tco) is not unreasonable.

Vaughn Altera

Reply to
Vaughn Betz

Hi,

It looks like out1 is a top-level output of your design. That means it is being implemented in an IO pad, and the delay you are getting includes the output pad delay driving the default load (10 pF for Stratix LVTTL IOs). That will be a significant delay. Also, there is a significant delay in getting the clock from the clock input pad (where the simulator monitors it) to the clock input of the various flip flops (unless you use a PLL).

So a ~5 ns delay (Tco) is not unreasonable.

Vaughn Altera

Reply to
Vaughn Betz

(snip)

I believe you are rising edge triggered, not falling edge.

That is, at least, what I see in my simulations.

-- glen

Reply to
glen herrmannsfeldt

Vaughn,

I gather then that to decrease this delay I would need to use the output of a PLL to feed the above process statement sensitivty list? If so, how could the PLL routing to the various flip flops be any different then going from the input pad? Would there be that much of a difference? Incidentally, this significantly dampers the overall speed at which the state-machine can operate.

Cheers, Pino

Reply to
Pino

Hi Pino,

If you're worried about the state machine delays you see in simulation, and you plan to use this on-chip (i.e. you're not sending the signals off chip in the final design) then add a register between each of your outputs and the top-level design output. Then the outputs you are monitoring will be on-chip, rather than off-chip, signals, and will have shorter delays.

Alternatively you could go to the Quartus node finder and find the name of the register output that is driving out1, and monitor that (again, it will be faster since it is before the output pad, which is your slowest part).

The delay of the output pad should not be limiting the speed of your state machine, although it would impact any downstream chip that was receiving this data. What does Quartus report as a maximum clock frequency for this clock domain? To get the best performance, make sure you have set a timing constraint on this clock, and that it is for a high speed.

As for a PLL decreasing the delay to the register inputs, that is done by generating a clock that is frequency matched to the input, but earlier in time. So a PLL does not decrease the routing delays; it shifts the clock in time to cancel out the routing delays.

Hope this helps,

Vaughn Altera

Reply to
Vaughn Betz

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