Altera PowerPlay Power estimation

Hi,

I am trying to evaluate the power consumption of one of my design. But the powerplay power analyser keeps telling me that the metric confidency is low, because much of the toggle rates are vectorless estimated (not computed based on real signal activities). Though, all the toggle rates should come from my VCD file (value change dump file) that I fill with Modelsim simulation. In the powerplay power analyser's report, I can see each signal, and wether its toggle rate has been estimated, or computed using the vcd file. Here is an exemple of what I can read :

mat_correl:matcorrel|mul_mgc_mul_pipe_1_z_oreg[0] Combinational cell Simulation file1 mat_correl:matcorrel|mul_mgc_mul_pipe_1_z_oreg[0]~feeder Combinational cell Vectorless estimation

I can trace back the first signal in my design, even in modelsim with a

find signals *pipe_1_z_oreg*

But I don't find any signal with "feeder" in the name. If someone could explain me why Quartus adds "ghost" signals with ~feeder at the end, it would help. I have the same problem with RTL or gate level simulation. Quartus 6.0 or 6.1.

many thanks in advance,

Alexandre.

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AG
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file1mat_correl:matcorrel|mul_mgc_mul_pipe_1_z_oreg[0]~feeder

Hi Alexandre,

The ~feeder cells are wire LUTs that Quartus introduces to allow either faster delivery of the data to the register or extra routing flexibility. In a gate level simulation, these extra node will be simulated, and you should get high confidence from the Quartus PowerPlay Power Analyzer.

You should be able to see both the original signal and the ~feeder signals in the ModelSim simulation if you have compiled the gate level netlist (.vo or .vho). This netlist is output by the Quartus EDA Netlist Writer. In this gate-level flow, if all of the appropriate simulation signals are dumped to the VCD file (and you can use the Quartus generated TCL script for this purpose), you should obtain a high confidence rating in the PowerPlay Power Analyzer.

If you are using RTL level simulation (where you are compiling your source code in ModelSim as opposed to using the gate-level netlist produced by Quartus), then these ~feeder signals will not be simulated. Actually, in an RTL level simulation, the Quartus PowerPlay Power Analyzer will only retrieve register and I/O signal activities, and the signal activities for the remaining combinational nodes will be filled in by vectorless estimation. This may be the issue you are having.

I hope this helps, and please let me know if you have further questions, Meghal

Reply to
mvaria

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