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Altera PLL and Timing Analysis

Dear all, I've placed my design in an Altera Stratix and use a PLL for clock generation. In a first stage PLL generated 22 MHz as output freq and Quartus II (3.0 release) showed 36 MHz as fmax. Due to this result, I have decided to increase PLL output to 33 MHz (without any change on the design). Now, after placement, Quartus Timing Analyzer shows 33.1 MHz as new fmax. I've repeated both placements (with a 22MHz PLL and with a 33 MHz PLL) multiple times and the results are similar.

Has the PLL configuration any impacts on other parameters which affect timings ?

I've also tried a backannotation when going to 33 MHz, but the results are the same. I can't use Chip Editor, since it crashes.

Thanks for your help.

Reply to
g. giachella
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Hi,

the placement of Quartus depends on many factors, changing the fmax-requirement (the PLL-output is used as fmax-requirement automatically for that clock by Quartus) will change the timing-driven-placement and therefore also the timing. You can vary the "Seed"-number in Assignments -> Settings -> Fitter Settings (or -> Compiler Settings -> Fitting in your version) to get other placements, with either better or worse timing. (DSE searches for the best seed automatically).

But why do you think that 33.1 MHz is not OK when you need 33MHz?

The chip-editor is more stable in newer Quartus-versions, I think.

Regards,

Thomas

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Reply to
Thomas Entner

Hi g. giachella,

First of all I suggest that you move to a newer version of Quartus. Version

3.0 is over a year and a half old (if not more) and the tool has improved considerably.

The PLL setting indeed affects Quartus' results because the placer picks paths to optimize based on the amount of slack (the difference between the reached and the desired frequency), and basically any difference in a design results in a different initial placement.

Quartus will attempt to meet timing, and will stop when it reaches timing or after a number of iterations hasn't found a workable solution (after which you will see errors in the timing report). I am pretty sure that if you set the PLL to output 36MHz, you will reach this performance.

As to the chip editor crashing, this subsystem was new in 3.0, and is stable in the current 4.2 version.

Best regards,

Ben Twijnstra

Reply to
Ben Twijnstra

Thomas and Ben, thank you for your answers.

timing or

which

you set

I have already tried that and, you are right, I' ve achieved that fmaxvalue.

My only fear is that, due to a possible Quartus underestimation of max delays (it is an old release), that margin (about 100 ps) could be not enough.

The design includes an vhdl IP core and associated scripts (for Quartus 3.0) and, in the past, Quartus newer releases had problems when reading directives written for older ones.

Again, thanks.

Reply to
g. giachella

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