To all,
Does anyone have a good document that describes the design of a Master Peripheral using the Avalon Bus for Altera Stratix Edition? I read in detail the Avalon Bus specification sheet, and when I try to develop the state machine to match the timing diagrams within the specification sheet, I manage to obtain significant delays (~ 10-11 ns) as a result of tpd within the chip, and therefore cannot align my waveforms as it is described in the document. The clock frequency I am using is 100 MHz, since I want to interface with the SDRAM controller and the NIOS development kit 16MB SDRAM. Does anyone know if this matters for the Avalon Bus? I mean does a timing misalignment in sending READ_N, ADDRESS, and BYTEENABLE_N for the read operation for instance matter greatly to the Avalon interface? Do I need to slow the interface down, and not use 100 MHz? Any suggestions on whether this sounds correct would be appreciated.....thus far, I wish there was better documentation on this so I had a better gutt feel on whether I'm implementing this correctly. Unfortuantely I only have the Quartus Environment as a simulator, and can't invoke Modelsim due to some license issues, I'm currently trying to get over.
Cheers, Pino