Altera / Lattice / Xilinx CPLDs ?

Laurent,

5V tolerance may be easily achieved by using external series resistors on the IO pins.

Is this OK?

Then, you may choose Altera, Lattice, or Xilinx solutions.

Austin

For my own senseless curiosity, would you mind mentioning the application? I'm wondering what new designs require the way-over-the-hill 5V standard. The continuing requirements for 5V interfaces baffle me.

My current favorite CPLD is Alter'a MAX-II. Vcc=1.8v, and from the data sheet:

"A MAX II device can drive a 5.0-V TTL device by connecting the VCCIO pins of the MAX II device to 3.3 V. This is possible because the output high voltage (VOH) of a 3.3-V interface meets the minimum high- level voltage of 2.4 V of a 5.0-V TTL device"

G.

John_H wrote: ...

For example to interface the Parallelport to a 1.8/2.5/3.3V Jtag Chain in a Byteblaster/Parallel Cable III way...

And configurable hysteresis like in the Coolrunner II comes in handy...

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

It's generally the 5V inputs where you run into trouble. 5V TTL usually drives up to 3.5 - 4 Volts under light load conditions.

5V CMOS pretty much drives to the 5V rail.

I like the Lattice MachXO "C" parts with the built-in core voltage regulator to allow 3.3V only operation even though the core runs at 1.2V

Input voltage tolerance is spec'd at 4.25V, not quite enough for 5V CMOS, but perhaps enough to avoid resistors on 5V TTL.

Internally MachXO is really an FPGA with fast self configuration from its own flash. The largest MachXO parts also contain some block RAM, which comes in handy. You didn't mention speed requirements, so you need to be careful if you want very fast pin-to-pin throughput, since this is not a traditional sum-of-products CPLD.

The parallel port is the only thing that initially came to mind for me. I understand there are still those who want that connection, but is this all of the 5V applications anymore or is the original poster looking for something else?

If do you think you will be able to run a CPLD IO at 1.8V at high speed and keep the 5V tolerant option (only for the inputs of course) using series resistors I think you have limited chance. Compute the delay induced by the parasitical capacitance of the input and the minimum resistor value and see, maybe it's ok. AFIK there is no other safe 5V tolerant device than those using 3.3V logic levels.

Vasile

If you use the AVR line of microcontrollers, most parts only guarantee to run at full speed at 5 Volt. Furthermore AVR Pins are not 5 Volt tolerant when running with 3.3 Volt.

Interfacing different voltages and partial power down is always a big concern in my designs. A 1.8/.../5 Volt CPLD would come handy...

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Laurent;

1) The Xilinx XC9500XL CPLDs have a VCCint of 3.3v; I/Os accept 5V, 3.3V, and 2.5V inputs; outputs 2.5v or 3.3v signals; each I/O has input hysteresis (all info from Xilinx datasheet). XC95144XL is closest part to your needs. Altera probably has something similar. 2) Use CRII along with voltage translators.

-Dave Pollum

Well, OK, here's one: We have a custom ASIC made through MOSIS in the

5V AMIS C5N process. It has 16 channels of traditional nuclear instrumentation front end, everything but the ADC. We are aiming for 14-bit resolution, and getting a real 12+ bits through the entire system. So, we use the 5V analog range to help us meet the 14-bit requirement. Admittedly, we are pushing CMOS just about as far as you can go for dynamic range. We have a 5V Xilinx CPLD on each board with two of the ASICs, and a 5V Spartan on the motherboard to decode and assemble control signals.

Jon