altera latch synthesis

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Hi all,

I'm working with Quartus II 2.2 sp2 and my target fpga is APEX20KE.
I have described a latch in my VHDL code with an enable signal, something
like this

library ieee;
use ieee.std_logic_1164.all;

entity my_lat is
    port (d : in std_logic;
          en : in std_logic;
          clk : in std_logic;
          q : out std_logic);
end my_lat;

architecture rtl of my_lat is
    signal next_q, q_local : std_logic;
begin
    next_q <= d when (en='1') else q_local;
    q_local <= next_q when (clk='1') else q_local;
    q <= q_local;
end rtl;

Quartus II synthesizes this code mapping the latch on a lut with the
following equation:

--A1L5 is q_local~1 at LC3_1_S1
--operation mode is normal
A1L5 = clk & (en & d # !en & A1L5) # !clk & A1L5;

The gate level backannotated simulation produces oscillation on q output.
Actually this what I see in a more complex design (this is only an example).
Looking the equations it seems to be all ok, even if SDF extracted doesn't
contain any TIMING CHECKS for combinatorial part of a LE, nevertheless the
equation describes a combinatorial loop.

(CELL
    (CELLTYPE "apex20ke_asynch_lcell" )
    (INSTANCE q_local_a16.lecomb )
    (DELAY
      (ABSOLUTE
        (PORT dataa (3754:3754:3754) (3754:3754:3754) )
        (PORT datab (11093:11093:11093) (11093:11093:11093) )
        (PORT datac (3754:3754:3754) (3754:3754:3754) )
        (PORT datad (274:274:274) (274:274:274) )
        (IOPATH dataa combout (800:800:800) (800:800:800) )
        (IOPATH datab combout (783:783:783) (783:783:783) )
        (IOPATH datac combout (726:726:726) (726:726:726) )
        (IOPATH datad combout (335:335:335) (335:335:335) )
      )
    )
  )


Any suggestion?

Thanks in advance,
Andrea



Re: altera latch synthesis
Hi all,

I have done some other investigations on the problem and I have a theory.
As I already mentioned in the previous message the latch has been
synthesized using a LUT of a LE. The SDF characterizes the lecomb by PORT
and IOPATH statements; no TIMING CHECK is present. For simplicity consider
EN signal statically at 1. If the D input has a transition just before the
falling edge of CLK (< PORT(D) delay) an oscilation occurs. The explanation
is the following: The D transition that occurs with CLK=1 throws a
transition on Q (=LE's combout) after PORT(D)+IOPATH(D) delay. Neverthless
the CLK causes the latch to hold Q value at CLK transition time after
PORT(CLK)+IOPATH(CLK). This triggers the oscillation.
Probably the situation is similar to setup time violation, but Quartus II
models the latch via a LUT an surely there is no trace of this trouble in
the static analysis.

Thanks,
Andrea




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example).
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Re: altera latch synthesis

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Do you really want a latch?  As you've seen, the architecure doesn't
support it directly, so it will get synthesised using luts.  The
static timing won't necesasrily be abel to handle it as it's an
asynchronous latch, so you'll be on your own timing wise.


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What was the question exactly?


Cheers,
Martin
--
snipped-for-privacy@trw.com
TRW Conekt, Solihull, UK
We've slightly trimmed the long signature. Click to see the full one.
Re: altera latch synthesis
I don't want to modify a complex VHDL code, moreover the architecture
pipeline needs latch to work properly without loosing performances.
What do you suggest?

Andrea


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something
output.
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doesn't
the



Re: altera latch synthesis
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Why not?
If there isn't a functional testbench, that is your first job.

Once you have a testbench, you can easily verify your changes.

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You can pipeline just as fast with D flops.
Use a PLL to double the clock if need be.

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Take the bull by the horns and design out the latches.

   -- Mike Treseler



Re: altera latch synthesis
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Hi Mike,
I think you are correct! This is the only one solution.
Thank you,

Andrea



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