Hi all,
I'm working with Quartus II 2.2 sp2 and my target fpga is APEX20KE. I have described a latch in my VHDL code with an enable signal, something like this
library ieee; use ieee.std_logic_1164.all;
entity my_lat is port (d : in std_logic; en : in std_logic; clk : in std_logic; q : out std_logic); end my_lat;
architecture rtl of my_lat is signal next_q, q_local : std_logic; begin next_q