Altera Flex10K Fast Output Register warning

Hello all I have a perfectly reasonnable design with bidir pins, written in the purest VHDL style: lberr_b

Reply to
Nicolas Matringe
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Hi Nicolas,

The FLEX 10K family only has one register in each IO cell. That means that with a bidirectional IO like you have, where both the dataout signal and the OE signal come from registers, only one register can be implemented in the IO cell itself. This won't affect functionality, but will increase your Tco for whatever signal doesn't go into the IO cell.

To get the best Tco, you can lock the other register (that doesn't get moved into the IO cell) to the LAB next to the IO cell, if the fitter hasn't done that automatically.

Stratix, Cyclone & beyond all have more registers in the IO cell, so you won't run into this issue with them.

Vaughn

Reply to
Vaughn Betz

Vaughn Betz a écrit :

Yes, I know all this (already got stung by this single IO register that did not show in the datasheet 6 years ago) What I don't understand is why Quartus refuses to put the output register in the IO when I ask it to do so (and put the input & tristate regs somewhere else)

I'm stuck with a Flex10K on this project

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Reply to
Nicolas Matringe

Nicolas,

Make the Fast Output Register assignment to lberr_b_out (the data output register) instead of lberr_b (the output IOC). I just tried this in Quartus version 4.2 on a sample design, and it worked fine.

Making a Fast Output Register assignment to pad tells Quartus to pack both the data & OE registers feeding the IO into the IO cell. Making the assignment to the data output register instead says that's the register you want packed in the IO cell, which is useful in this case since Quartus can't pack both the OE & data registers in the IO cell for the FLEX 10K.

Regards,

Vaughn Altera [v b e t z (at) altera.com]

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Reply to
Vaughn Betz

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