Altera FIR Compiler with clock enable

Has anyone had problems with Altera FIR Compiler generated cores when using the clock enable signal?

Have a look at my post at :

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I am trying to get a programmable coefficient filter to work with a clock enable, however I get a strange response. I have tried versions

3.3.0, 3.3.1 and 6.1 of FIR compiler. I understand that as of 6.1 the Avalon-ST controller is used which is independent of the global clock enable and is probably causing problems. However v3.3.0 and v3.3.1 are also giving problems, as I show in the post. The only FIR I can get to work with the clock enable is a fixed coefficient filter generated by v3.3.0. Unfortunately Altera support are not offering good advice on this issue.
Reply to
Wilhelm.Klink
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Hi Wilhelm,

There was a bug in earlier versions of the FIR compiler in that it relied on clock enable being high immediately after reset. If clock enable was low, the coefficient address logic would run anyway for a clock cycle, with the result that all coefficients were misaligned to the samples. With Avalon ST, clock enable would be held low until enough input samples were available, which could therefore exercise this bug.

Our IP group strongly recommends upgrading to version 7.1 of the FIR compiler, which has a more robust coefficient reload. You can download it from here

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Hope this helps.

Regards,

Vaughn Betz Altera

Reply to
vbetz

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enableand is probably causing problems. However v3.3.0 and v3.3.1

low, the coefficient address logic would run anyway for a

here

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The problem exists for both programmable and fixed coefficient filters in version 7.1 of the FIR compiler.

Reply to
Wilhelm.Klink

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