Has anyone had problems with Altera FIR Compiler generated cores when using the clock enable signal?
Have a look at my post at :
I am trying to get a programmable coefficient filter to work with a clock enable, however I get a strange response. I have tried versions
3.3.0, 3.3.1 and 6.1 of FIR compiler. I understand that as of 6.1 the Avalon-ST controller is used which is independent of the global clock enable and is probably causing problems. However v3.3.0 and v3.3.1 are also giving problems, as I show in the post. The only FIR I can get to work with the clock enable is a fixed coefficient filter generated by v3.3.0. Unfortunately Altera support are not offering good advice on this issue.