Altera Excalibur EBI problem

BlankHi, I seem to have a problem talking to a MAC chip that is connected as a memory mapped device on the EBI bus of an EPXA1-672 chip (EBI2 for CS, no split reads and no prefetch). EBI1 is connected to a flash chip. I am using the GNU toolset to develop code and no OS (as yet).

Apparently, if I read a single register (in my code), a series of 16 read accesses are made by the chip and cached. Subsequent reads do not access the MAC, rather return values from the cache - I do not see any CS transitions at the chip pins. The write operations function perfectly well if I do not perform a read - one CS for every write request. Once a read is performed, the writes also cease to be "executed" and change the register value in the cache only.

Has anyone seen a similar problem? The Altera folks have not responded to my trouble tickets - their support is not what it used to be.

Thanks, bta3

Reply to
bta3
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You have that area of the memory mapped cached ... you are seeing a cache line burst for the first access and nothing after that because it is manipulating the cache memory ... turn off the cache for this memory region.

Mike

Reply to
Mike Lewis

Thanks Mike.

Now if there is a way to turn off the DCache register in C rather than in assembly.....

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Reply to
bta3

I doubt if anyone has seen a similar problem. You wanna know why? Because no one actually bought and used the Excalibur chip. I am amazed to see a post about it.

Just wanted to let you know it is probably the biggest failed FPGA product in recent history and maybe in all of FPGA history. It probably cost around $100 million to develop. Earned around $0 million in sales.

Do yourself a favor and go get yourself a Virtex 4 FX development kit. PowerPC with embedded 10/100/1G Emacs. Now that is a device people will use in large numbers.

bta3 wrote:

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Reply to
seannstifler69

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