Altera equivalent for Xilinx's "async_reg" attribute

Hello The question is in the subject: is there such a thing? How to make an Altera post-p&r simulation work when a setup violation occurs on an input register?

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Nicolas Matringe
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-- Mike Treseler

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MikeTreseler

How about synching the testbench data output to the chip input clock? I don't think there is any value to allowing the setup time to be violated in a simulation since there is no simulation equivalent to metastability.

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Rick "rickman" Collins

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rickman

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