Quite a simple question: how to simulate the DDR-SDRAM core from Altera in NCSim. I just can 't figure it out though Altera *claims* to support NCSim. To me it looks like their development chain is realy ModelSim/Quartus only...
The things I've tried:
- simulate netlist from core (yes I've got a license) : doesnt' work due to errors when trying to compile the thing.
- dump a "functional description" of the core: works but I'm missing some important functionality like burst length settings and so on. The IP generation tool doesn't seem to work in Linux so it's switching back and forth to Windows when I want to change something in the core.
Anyone a sollution? To Altera: lovely FPGA's but quite crapy software (did I mention how many times Quartus crashes in Windows?). Sorry to say that.
Jan