All of the design is being optimized away and logic removed

I using the Xilixn tool flow. After synthesis with XST, the synthesis report looks fine, it contains all the Flip flops, adders etc. The next step of translation also goes well without errors or warnings. However, durinng the mapping phase all my design is removed as redundant logic. Any Ideas as to what I am doing wrong??

Reply to
azam
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I using the Xilinx tool flow. After synthesis with XST, the synthesis report looks fine, it contains all the Flip flops, adders etc. The next step of translation also goes well without errors or warnings. However, during the map phase all my design is removed as redundant logic. Any Ideas as to what I am doing wrong??

Reply to
azam

Azam,

This is what i can think of: (*) You are not using manual instantiation of I/O buffers, and Add I/O buffers option is turned off, in which this case, you should get many warnings during MAP, somehting like " Attribute LOC is on the wrong type of object "... But you said no warnings or errors, so....

(**) The design can have logic which does not go outside or simply unconnected. If this is a major signal, like clock, then eventually everything is being optimizes away.

Can you paste the MAP report?

Vladislav

Reply to
Vladislav Muravin

Look at the map report (*.mrp). There is a section that shows the trimmed logic. The lines beginning in the leftmost columns are the root of everything under them that gets pulled out. Usually this is because of an output that is unconnected, or perhaps a clock enable that is always zero. The map report is the secret to figuring out what caused everything to get ripped out.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Reply to
Ray Andraka

Vladislav,

The warnings are related to the I/O's of my top level module.

Release 7.1.03i Map H.41 Xilinx Mapping Report File for Design 'sata_device_gasket'

Design Information

------------------ Command Line : C:/Xilinx_71i/bin/nt/map.exe -ise e:\gasket_xilinx\gasket_xilinx.ise -intstyle ise -p xc4vlx40-ff668-11

-timing

-ol high -t 1 -register_duplication -cm speed -detail

-ignore_keep_hierarchy -pr b -u -k 4 -c 100 -o sata_device_gasket_map.ncd sata_device_gasket.ngd sata_device_gasket.pcf Target Device : xc4vlx40 Target Package : ff668 Target Speed : -11 Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ Mapped Date : Wed Jul 20 10:42:22 2005

Design Summary

-------------- Number of errors: 0 Number of warnings: 87 Logic Utilization: Number of Slice Flip Flops: 573 out of 36,864 1% Number of 4 input LUTs: 1,296 out of 36,864 3% Logic Distribution: Number of occupied Slices: 865 out of

18,432 4% Number of Slices containing only related logic: 865 out of 865 100% Number of Slices containing unrelated logic: 0 out of 865 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 1,304 out of 36,864 3% Number used as logic: 1,296 Number used as a route-thru: 4 Number used as Shift registers: 4

Total equivalent gate count for design: 13,582 Peak Memory Usage: 291 MB

Table of Contents

----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group Summary Section 10 - Modular Design Summary Section 11 - Timing Report Section 12 - Configuration String Information Section 13 - Additional Device Resource Counts

Section 1 - Errors

------------------

Section 2 - Warnings

-------------------- WARNING:Map:120 - The command line option -c can not be used when running in timing mode. The option will be ignored. WARNING:LIT:243 - Logical network mrconStart has no load. WARNING:LIT:243 - Logical network rst_spd_chng_en has no load. WARNING:LIT:243 - Logical network genAlign_i has no load. WARNING:LIT:243 - Logical network AGS_en has no load. WARNING:LIT:243 - Logical network pllClkDiv5 has no load. WARNING:LIT:243 - Logical network pwrdnBiasGeno has no load. WARNING:LIT:243 - Logical network pwrdnPLLBo has no load. WARNING:LIT:243 - Logical network snoozePHYo has no load. WARNING:LIT:243 - Logical network snoozePHYo has no load. WARNING:LIT:243 - Logical network comType has no load. WARNING:LIT:243 - Logical network comType has no load. WARNING:LIT:243 - Logical network pwrdnTxBo has no load. WARNING:LIT:243 - Logical network pwrdnTxBo has no load. WARNING:LIT:243 - Logical network resetDigToPHYB has no load. WARNING:LIT:243 - Logical network resetDigToPHYB has no load. WARNING:LIT:243 - Logical network pwrdnTxDrvBo has no load. WARNING:LIT:243 - Logical network pwrdnTxDrvBo has no load. WARNING:LIT:243 - Logical network pwrdnDetBo has no load. WARNING:LIT:243 - Logical network pwrdnDetBo has no load. WARNING:LIT:243 - Logical network forceIdle has no load. WARNING:LIT:243 - Logical network forceIdle has no load. WARNING:LIT:243 - Logical network offlinePHYo has no load. WARNING:LIT:243 - Logical network offlinePHYo has no load. WARNING:LIT:243 - Logical network partialPHYo has no load. WARNING:LIT:243 - Logical network partialPHYo has no load. WARNING:LIT:243 - Logical network txDataToPHY_0 has no load. WARNING:LIT:243 - Logical network txDataToPHY_0 has no load. WARNING:LIT:243 - Logical network txDataToPHY_0 has no load. WARNING:LIT:243 - Logical network txDataToPHY_0 has no load. WARNING:LIT:243 - Logical network txDataToPHY_0 has no load. WARNING:LIT:243 - Logical network txDataToPHY_0 has no load. WARNING:LIT:243 - Logical network txDataToPHY_0 has no load. WARNING:LIT:243 - Logical network txDataToPHY_0 has no load. WARNING:LIT:243 - Logical network txDataToPHY_0 has no load. WARNING:LIT:243 - Logical network txDataToPHY_0 has no load. WARNING:LIT:243 - Logical network txDataToPHY_1 has no load. WARNING:LIT:243 - Logical network txDataToPHY_1 has no load. WARNING:LIT:243 - Logical network txDataToPHY_1 has no load. WARNING:LIT:243 - Logical network txDataToPHY_1 has no load. WARNING:LIT:243 - Logical network txDataToPHY_1 has no load. WARNING:LIT:243 - Logical network txDataToPHY_1 has no load. WARNING:LIT:243 - Logical network txDataToPHY_1 has no load. WARNING:LIT:243 - Logical network txDataToPHY_1 has no load. WARNING:LIT:243 - Logical network txDataToPHY_1 has no load. WARNING:LIT:243 - Logical network txDataToPHY_1 has no load. WARNING:LIT:243 - Logical network comStart has no load. WARNING:LIT:243 - Logical network comStart has no load. WARNING:LIT:243 - Logical network rxDataToLL_0 has no load. WARNING:LIT:243 - Logical network rxDataToLL_0 has no load. WARNING:LIT:243 - Logical network rxDataToLL_0 has no load. WARNING:LIT:243 - Logical network rxDataToLL_0 has no load. WARNING:LIT:243 - Logical network rxDataToLL_0 has no load. WARNING:LIT:243 - Logical network rxDataToLL_0 has no load. WARNING:LIT:243 - Logical network rxDataToLL_0 has no load. WARNING:LIT:243 - Logical network rxDataToLL_0 has no load. WARNING:LIT:243 - Logical network rxDataToLL_0 has no load. WARNING:LIT:243 - Logical network rxDataToLL_0 has no load. WARNING:LIT:243 - Logical network slumberPHYo has no load. WARNING:LIT:243 - Logical network slumberPHYo has no load. WARNING:LIT:243 - Logical network rxDataToLL_1 has no load. WARNING:LIT:243 - Logical network rxDataToLL_1 has no load. WARNING:LIT:243 - Logical network rxDataToLL_1 has no load. WARNING:LIT:243 - Logical network rxDataToLL_1 has no load. WARNING:LIT:243 - Logical network rxDataToLL_1 has no load. WARNING:LIT:243 - Logical network rxDataToLL_1 has no load. WARNING:LIT:243 - Logical network rxDataToLL_1 has no load. WARNING:LIT:243 - Logical network rxDataToLL_1 has no load. WARNING:LIT:243 - Logical network rxDataToLL_1 has no load. WARNING:LIT:243 - Logical network rxDataToLL_1 has no load. WARNING:LIT:243 - Logical network resetCDRToPHYB has no load. WARNING:LIT:243 - Logical network resetCDRToPHYB has no load. WARNING:LIT:243 - Logical network pwrdnRxBo has no load. WARNING:LIT:243 - Logical network pwrdnRxBo has no load. WARNING:LIT:243 - Logical network halfRateToPHY has no load. WARNING:LIT:243 - Logical network halfRateToPHY has no load. WARNING:LIT:243 - Logical network phyrdy has no load. WARNING:LIT:243 - Logical network phyrdy has no load. WARNING:LIT:243 - Logical network txSigSel_0 has no load. WARNING:LIT:243 - Logical network txSigSel_0 has no load. WARNING:LIT:243 - Logical network txSigSel_1 has no load. WARNING:LIT:243 - Logical network txSigSel_1 has no load. WARNING:LIT:243 - Logical network genD10_2_i has no load. WARNING:LIT:243 - Logical network spareIn has no load. WARNING:LIT:243 - Logical network spareIn has no load. WARNING:LIT:243 - Logical network spareOut has no load. WARNING:LIT:243 - Logical network spareOut has no load.

Reply to
azam

The best option for you is to add IO buffers to inputs and outputs in synthesis stage. This can be done by specifying the "add IO Buffers" in the "Xilinx Specific Options" tab of XST properties. If your design is such that you do not want to add IO buffers (that is to not connect your signals externally), then you should unset the "Trim Unconnected Signal" option in Map properties.

Love Singhal

Reply to
Love Singhal

Dear Azam,

I can think of only missing I/O buffers, so you need to tuirn on "Add I/O Buffers" option in XST synthesis options. But there supposed to be a section which says exactly what logic has been optimized (i think it's called "trimmed")

Are you still having this issue?

Regards, Vladislav

Reply to
Vladislav Muravin

Hello Vladislav, Singhal and Andraka,

As this is not my top-level design I did not want IOB assigned, then I turned off the trim unconnected signals. This way the tool does not remove away all the logic.

Thanks fls for all the help.

-Azam

Vladislav Murav> Dear Azam,

Reply to
azam

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