I am using a virtex 4. I have an clock input, and another input for bitstream. What is the best way to align the rising edge of a bit to the rising edge of a clock? It needs very quick. Currently I am using IDELAY to shift the data until I notice no bit errors, but it is taking up to 500ms.
Is your bitstream synchronous with the input clock?
You could try sychronizing your data using two (or three) D-type FF, such that the rising edge of the input clock, clocks the data into the first FF, then into the second on the next rising edge. This will allow the first FF (if the bit stream is not 100% synchronous) to stabilize before entering the second FF before allowing to pass to the bitstream decode locic.
You will have a 2 clock delay.
You can also use the DDR register to make the synchronized bitstream and clock souce synchronous.
Clock the DDR register with the same input clock, tie one of the DDR's inputs to Logic 1 and the other to 0, and also clock your bitstream through a FF using the same input clock. Set the constraints to keep the all that logic in the same area.
I've done this in the past for asynchronous signals and it worked okay.
You may also want to look in to the DCM, though i have less expeirence with the DCM and there full capabilities in the Vertix 4.
Hope this helps.
--Brian
What is the best way to align the rising edge of a bit to the rising edge of a clock? It needs very quick. Currently I am using IDELAY to shift the data until I notice no bit errors, but it is taking up to 500ms.
If the data and clock aren't synchronized most of the time, how is adjusting the delays going to help? Or do you mean "not aligning the sampling clock to the center of the bit" rather than "exact same frequency/bit rate, just an unknown phase?" Synchronous items are at the same frequency. Precisely. If there's a phase/freq modulation on one synchronous item, the same phase/freq modulation should be on the other.
What are the data and clock rates you're working with?
Is it a high speed application where the data is a constant bit rate but you only have a solid asynchronous clock to work from? Do you have multiple bits to synchronize? If so, I'll point out the App note.
I meant the data and the clock is just out of phase initially. It is a biphase mark code I am workign with. I have recovered the clock, but the bits may be out of phase when I sample, so I need to delay either the clock or the bitstream. It will stay aligned after that until the stream is broken.
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