Hello, I've got a Xilinx Virtex 4 FPGA and would like to address the onboard DDR-SDRAM. I've found out that I can instantiate special DDR-IO flip flops by hand (and found an example in the ISE-Webpack documentation). But I'm still not sure how to address the DDR-SDRAM best, especially I don't know how to handle the DQS-Signal of the DDR-SDRAM, because I need a sensitivity on both edges.
Perhaps someone can even help me with a short example (VHDL preferred).
Thanks in advance,
Thomas