I have this vhdl source:
-----------------8
I have this vhdl source:
-----------------8
Mastupristi a écrit:
[...]Your signal is not used anywhere so it is optimized away.
-- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
Your module does not have an output signal, so I assume that the synthisizer synthisized the entire module away... try the following code:
entity lupicrudi is Port ( clk : in std_logic count : out std_logic_vector (7 downto 0)); end lupicrudi;
architecture Behavioral of lupicrudi is
signal count: std_logic_vector(7 downto 0);
begin
process (clk) begin if rising_edge(clk) then
count
sorry I had a typo
use the following code :
entity lupicrudi is Port ( clk : in std_logic coun_out : out std_logic_vector (7 downto 0)); end lupicrudi;
architecture Behavioral of lupicrudi is signal count: std_logic_vector(7 downto 0); begin process (clk) begin if rising_edge(clk) then
count
How to avoid the optimization of this signal? I use it only for debug purpose so I don't want (and I don't have space) to put it out.
thanks
--=20 Mastupristi?
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.