I am having a problem with the timing on our new board. I need to delay one of the output signals from my cpld by 80nS. Im not that familiar with using the altera quartus software, all the timing issues it talks about is to speed it up. Is there a way of adding a delay, i've also tried adding a delay into a vhdl block but it is having no effect! i would b grateful for any help paul
80ns is a long delay. What's your clock speed? You could make a shift register using a chain of flip flops or even use a counter. Failing that, you could cascade several I/O block delays i.e. go off- and back on-chip a few times. You might even consider buying a passive delay line.
Delay is not synthesizable, that's why it is not having any effect. Prevailing FPGA design philosophy today is that it has to be synchronous, i.e. everything that happens in the FPGA has to happen on a clock edge. Thus, having a clock is essential. Look at what kind of clocks you have in your design and see whether you can achieve what you need by pipelining your output signal.
/Mikhail
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