Hi all, Can anyone tell me why this occurs : "when synthetizing we get a good results (time/area) by using an adder contained in the fpga circuit and when we use an adder that can be manually designed, we get a less performances (time/area) " ? Thanks.
nezhate schrieb:
Hi, It's quite simple: Imagine in vhdl you write a behavioral statement like
y
The adder in the FPGA is a silicon-optimized solution that uses embedded carry chains with very low propagation delays to perform the function. This optimized silicon is used because this is a common FPGA design element that has too many levels of logic for a "manual design" to implement well with the delays between LUTs. The manual design also requires a carry chain set of LUTs to complement the result LUTs.
Read up on the FPGA's implementation of carry chains and you'll find dedicated silicon to handle the speed and density.
The synthesis software knows more about the target FPGA than whoever is doing the manual design. If the manual designer learnt the details of the structure of the FPGA, then the manual designer could equal the results of the synthesis software. For the case of an adder, it would be rare that the manual designer could do better than synthesis. For other more complex structures, the manual designer could do better but would require detailed understanding of the target FPGA.
=================== Philip Freidin snipped-for-privacy@fpga-faq.org Host for
If you are pushing the envelope at all, you probably need that detailed understanding so you can do a sanity check on the compiler. If it isn't doing a good job you may want to tweak your code so the compiler will recognize your pattern, or maybe just instantiate what you want.
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