ADC Interleaving

I mean you want to reach 500MS/s sampling?

It could be possible, you must be careful in designing PCB,

Jerzy Gbur

In general, you will find that this is a lot of trouble.

That said, it is done. See the AD12401 at

If you want to interleave multiple ADCs there are three main parameters that must be matched or corrected for on the ADCs. To the extent that they are not matched, the quality will degrade.

1. DC offset. Easy to track and remove if it is not matched.
2. Gain. Needs to be matched or equalized across your frequency range of interest.
3. Sampling phase offset. This is the one that will cause you big problems. If the ADCs have any phase error in when they sample, it will cause spurs in the data. The hight of the spurs depends on the sampling phase error. The data sheet for the AD9481 gives an error budget of < 2 ps for interleaving two 8 bit 250 MS/s ADCs with a 100MHz analog input. That error budget will go down if your analog input is higher frequency, or if you want more bits of resolution.

I think that there are some graphs of sampling phase error budgets vs other parameters some where on the Analog web site, but I do not remember where.

Regards,

John McCaskill

Yes I would like to reach that sampling, but I guess there are a lot o other things to take into consideration apart from the pcb like the AD errors etc.

Cheers

Jon