ADC capture with FPGA Spartan3 in Verilg

Hello, This source is a capture the ADC0804 with FPGA Spartan3, Oscillator 50MHz frequency Clk for ADC is 650KHz, sampling frequency 8Hz, show the data capture in array leds.

//##############adc08.v################### //#########Develp by Jhoberg Quevedo############ //#########email: snipped-for-privacy@gmail.com###########

module adc08(clkadc,adc,adccs,adcwr,adcintr,led,osc); parameter Nosc=32; input osc; input adcintr; input [7:0] adc; output clkadc; output adccs; output adcwr; output [7:0] led;

reg clkadc; reg adccs; reg adcwr;

reg [7:0] dato; reg [7:0] led; reg [Nosc:0] tcont; reg [7:0] tclk;

always @(posedge osc) begin tcont=tcont+1; tclk=tclk+1; if(tcont==6250000) begin tcont=0; if (adccs) begin adccs=0; adcwr=0;

end else begin adccs=1; adcwr=1; end end if (tclk==77) begin tclk=0; if (clkadc) clkadc=0; else clkadc=1; end

end

always @(posedge adcintr) begin led=adc; end

endmodule

#####################adc08.v#####################

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