When I evaluated Active-HDL this past summer (7.2sp1), I liked the user-interface more than Modelsim. However, Aldec's Systemverilog support was quite far behind Modelsim 6.2g.
Now, I was wondering how these two products compare, today. Looking at Aldec's online manual, it seems Active-HDL 7.3 has caught up with Modelsim PE. (PE still supports some constructs that Aldec doesn't, but Aldec has rudimentary support for classes.)
Performance-wise which is faster? (Most likely, my decision is between Active-HDL "Plus Edition" and Modelsim-PE.)
Any problems with the Smartmodel/LMTV interface? (This is standard for Modelsim/PE, but a separate upgrade for Active-HDL Plus-Edition.)
And a final question. I know that Xilinx/Altera's development-suite officially support the Modelsim simulator. For example, the Xilinx EDK can autogenerate control-scripts and autolaunch a Modelsim session. Does Active-HDL have the same level of integration with Xilinx/Altera's development environment?
Smartmodels are not standard with Modelsim-PE. You can get them, but it is an additional license at additional cost. Did someone tell you it was standard with PE? They are standard with SE.
You can get a list of what each version of ModelSim supports here:
That is wierd -- I could have sworn the product-sheet showed PE with Smartmodel as a standard feature.
Many of Xilinx's IP-blocks (Rocket I/O GTP, Virtex4/5 TEMAC, PowerPC) require a Smartmodel capable simulator -- I've used PE 6.3c to simulate several TEMAC/PowerPC based Xilinx FPGA designs.
I was pretty sure PE supported Smartmodels, since I had to edit the modelsim.ini file to read in the Xilinx-provided Smartmodel/LMTV binaries. Or perhaps Xilinx used a special-wrapper, such that their sim-models look and act like conventional Verilog-PLI?
You can use Smartmodels with ModelSim PE, you just need to get a license for it. Look in the license file on the computer that you used to see if it had a license. I use ModelSim PE with extra license for Smartmodels, mixed language support, and code coverage. Even with getting the extra licenses PE was much cheaper than SE. Most of the difference is because of using a dongle instead of a floating license. SE comes standard with a floating license.
EDK supports ModelSim, and Cadence, but not Aldec.
Xilinx works with VCS-MX also and probably all decent simulatorns on all platforms, we use it on AMDs running Solaris 10 where Xilinx is not supported, see below for supported simulators on Sparc Solaris 10!
edaadm@brera $ compxlib -help sim Release 9.2.04i - COMPXLIB J.40 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
-s : Specify the name of the simulator for which the libraries are to be compiled. The valid simulator names are :-
mti_se mti_pe vcs_mx vcs_mxi ncsim
Also compiling is trivial in Verilog(just compile it), and in VHDL Xilinx has supplied a file named vhdl_analyze_order in the $XILINX/vhdl/src/XilinxCoreLib directory.
The OP asked what EDK supports, compxlib is part of ISE, not EDK. I am currently using EDK/ISE 8.1 8.2 and 9.1, and I see that ISE does support vcs, but EDK does not. I also use ModelSim but not Cadence.
When I say that EDK supports ModelSim and Cadence, I mean two things.
For those simulators the SimGen tool will generate setup scripts for you from your EDK project that let you launch the simulator, compile the project, setup the display windows, and run the simulation. I think that this is a very nice feature, but if you prefer another simulator, you can of course do this yourself.
Xilinx presumably does quality assurance testing against the simulators that they say are supported, and will provide help if you have problems. To me this is the critical point.
At least for ModelSim, Xilinx is very specific about which versions they support. In the case of EDK 8.2, they specify one specific release of ModelSim as the only supported version. We have tried running with other versions with mixed results. When we used the supported version, our test benches passed and matched what we saw in hardware. When we used other versions, some times we got the same results, some times we did not.
If your setup is working for you, I don't blame you for not wanting to change it. But there is a difference between it works, and it is supported.
As luck would have it I just got a call from someone at Mentor Graphics so I asked them about this. What they told me is that if you are using only Verilog in your design, you do not need the extra license for Smartmodels. If you are using any VHDL, you do need the license. When I asked why, they said that they would have to ask someone else and get back to me.
I did not run any mixed VHDL+Verilog simulations using the Xilinx Smartmodels, (only pure Verilog). So I gues lucky for me, I didn't run into this problem.
My guess is that with Verilog the "calls to external stuff" (PLI) is built into the core, with VHDL the Foreign Language Interface is an extra which is more simulator specific. And hence they can charge you for a more expensive license...
Cheers, Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
I accidentally confirmed this yesterday in conversation with someone from Mentor's UK distributor (Saros). SmartModels are accessed from VHDL through the "Swift Interface" and this is the [reason|excuse] for the extra license charge. I believe the dual-language license also allows access from VHDL (or Verilog) without additional charge.
Well, as an update to my rushed mini-review, here's what I've found so far:
a) The web-eval of Active-HDL 7.3 appears to run the "EE" product configuration, which is the most advanced edition of Active-HDL. Capacity is limited to
5MB or less, and sim-runtime is limited to 10us.
b) Modelsim/PE's Systemverilog (Design) support is more robust than ActiveHDL's. Just about everything I tried worked properly. Active-HDL 7.3 has a bunch of rough-edges. String types don't work properly with some standard system-tasks ($swrite, $sformat) -- there is no package/endpackage support (maybe that's in the full/commercial version?) And minor quirks in the Systemverilog preprocessor (string-concatenation doesn't trim whitespace: `define( myword ) `" blah myword blah `"
c) SVA (Systemverilog Assertion) constructs compiled and simulated successfully. Modelsim/PE doesn't do SVA at all. Active/HDL is the least expensive solution for designers wanting to use SVA in design. ('least expensive' does not mean cheap: Active/HDL-EE's SVA-option costs extra, and EE's base-price is 2X the price of Modelsim/PE!)
d) I tried a Xilinx Smartmodel based simulation (TEMAC from Coregen
9.2i.04), and with help from this usenet group, finally built the PLI and testbench properly. Unfortunately, I can't determine if its working properly, because the simulator terminates at 10us, long before that sim-testbench has a chance to finish.)
e) I didn't like the terseness of the assertion-$error/$warning/$info reports in the logfile. Unlike Modelsim, ActiveHDL does not stamp each message with filename/line# info. On the other hand, Aldec's GUI-console window is 'hyperlinked' -- doubleclicking on virtually any message (user or simulator generated) jumps the RTL-browser to the triggering statement, brilliant!
f) I couldn't check performance -- I didn't have a useful testcase which could finish in under 10us of simtime. And I don't have access to Modelsim/PE anymore.
g) ActiveHDL claims support for *some* Systemverilog testbench features -- but 'class/endclass' support isn't sufficient to do a heavy-duty TLM testbench. To be fair, Mentor restricts class/endclass (and assertions, coverage, etc.) to Modelsim/SE Questasim.
Overall, despite Modelsim/PE's advantages (more mature Systemverilog-Design support, and Xilinx/Altera's official blessing for FPGA-device sims), I'm leaning toward Active/HDL. The user-interface is much nicer (for me), and the existing Systemverilog support is quite usable for a small/FPGA project.
!!! That kind of version-dependency annoys/disturbs me. Why can't Xilinx just make/test their libraries with all versions /forward/ of a specific revision (like 6.1e or later)?
Looks like I'll hvae to run some EDK-simulation tests with Active-HDL, and see what problems (if any) I encounter.
By the way, thank you for your cautionary perspective. All too often, I take forgranted that "if version x is verified working, and y > x, then version y ought to work too." Bzzt -- false!
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