ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?

Hi, we do not succeed in compiling our design using mixed voltage I/O macros in ACTEL Designer 6.2 (SP2). To illustrate the problem, we have reduced it to a simple 2-input AND gate . (If someone wants to try we have attached the VHDL and the edif files below.) The error message is : Error: A mixed-voltage I/O macro is found in the design. This macro type is not supported. When Vddp = 2.5V, use XX25LPXX macro. When Vddp = 3.3V, use XX33XX I/O macro.

Please contact Actel Technical Support at 1-800-262-1060 or snipped-for-privacy@actel.com for more information.

According to the documentation, application notes and knowledge base on the ACTEL website, we were lead to believe that the device apa-150 powered with VDDp=3.3V is able to drive or receive both 2.5 and 3.3V compatible signals (except for the 25LP macros). Has anyone encountered this problem or know how to solve it ?

regards, J . Buytaert CERN, Geneva

VHDL:

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use work.apa_comps.all;

entity test1 is port( in1,in2 : in std_logic; out1 :out std_logic ); end;

architecture arch of test1 is component ib25S port( Y : out std_logic; PAD : in std_logic ); end component; component ob33PH port( A : in std_logic; PAD : out std_logic ); end component; signal in1b, in2b, out1b : std_logic;

begin out1b

Reply to
J buytaert
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The APA devices can't have mixed voltage I/O. Table 1-3 on page 1-9 of the datasheet (5.0) clearly shows that with VDDP of 3.3V, then the input compatability & output drive are both 3.3V. To get around the problem you need to use external components to change the logic levels.

Regards,

Neill.

J buytaert wrote:

Reply to
Neill A

"J buytaert" schrieb im Newsbeitrag news:di2v3o$7m2$ snipped-for-privacy@sunnews.cern.ch...

macros

datasheet reading skills:

PA+ DS, page 1-9 top righ corner table

at any given vddp there is only 1 standard supported either 2.5 or 3.3

this also understandable as we there are know (ASFAIK) FPGAs available that would support 2.5 drive from 3.3V IO voltage.

think of AP+ as a device with single IO bank, all IOs are using same IO voltage.

for your application you most likely can safely use 3.3V io macros even when the other end is 2.5 drive

Antti

Reply to
Antti Lukats

It seems to be a bit more suttle than that. In the data sheet mentioned is stated on page 1: "2.5 V/3.3 V Support with Individually Selectable Voltage and Slew Rate"

You can see in the revision history of the of the application note of the I/O Features one can see that the 3.3/2.5 V I/O mixing was included in an earlier version of the application note. Moreover, the knowledge database describes how to implement it (which is what we tried and it doesn't work).

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And the macro library guide

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states on e.g. page 62 which combinations of 2.5 and 3.3 V operation that is supported.

Hence reading the documentation it is supported or at least has been supported. The question we have is if someone knows a workaround, if the feature has been supressed or knows why the Actel Designer compiler doen't accept something that is described in the library guide.

Reply to
J buytaert

OK, I see why you were confused now. I've had a quick look, and I actually have a copy of the app note which talks about mixed voltage I/O, but it doesn't really say much more than you already seem to know.

Also after a quick check of the release notes for SP2, it seems this is where the problem is:

Mixed mode I/O support has been removed from APA devices. As of SP2, use of any of these mixed mode I/Os is prohibited: OB25XX, IOB25XX, IOBL25XX, OTB25XX, OTBL25XX, or IB25XX. If any of these I/Os are detected in an existing ADB, an error message appears, and alternative non mixed-mode I/Os are suggested.

So I guess the solution would be to uninstall SP2.

Reply to
Neill A

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