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Actel Libero upgrade - problem with clk pin - Synplify

Good morning,

I had a design wich was working fine in Libero 6.0 SP3 (Synplify

7.51A). I made an upgrade to Libero 6.2 SP2 (Synplify 8.1A). When I open the project the conversion works fine. Without changing anything to the vhdl files or viewdraw schematic file I redo the synthesis with Synplify. It seems to work without problem. I then open Designer. I get the following error message: Error: ERROR in SECTION GLOBAL_CLOCKS near line 17 :: DCF#023: Invalid pin Z_1I478:PAD. Pin is Ignored Warning: The constraint data (DCF) has unavailable net/pin references. The invalid constraints will be removed. I did not change anything to the clock pins! I prevent Synplify to use automatically all clock pins (HCLK, CLKA and CLKB) for all the clocks it finds in the design by adding two attribute lines (syn_noclockbuf...) in the vhd file created by viewdraw. And I use a CLKBUF in viewdraw to be allowed to set my clock signal on the CLKA pin. I am almost certain the problem comes from Synplify because if I do exactly the same steps but without redoing the synthesis, that is opening Designer directly after the conversion of the project then I get not error during the layout. Is there maybe an option in Synplify I have to change?

Thank you very much,

Marie

Reply to
Marie
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I have noticed that Synplify 8.1A seems to name things differently to

7.51A, so it might just be that you need to change the name in the DCF file.

Marie wrote:

Reply to
Neill A

Thank you for your reply. I do not find any .dcf file in my project directory. The .sdc constraint file seems empty. Could you tell me where I have to search? And when I will found this file which name should I change?

Thank you very much,

Marie

Reply to
Marie

OK, I just assumed that you were using a dcf file since that is what the error message reffered to. You could try reimporting your source files into designer, but ensure the little tick box for keep exisiting timing constraints is unticked. Then if it compiles you can then set up your timing constraints again.

Reply to
Neill A

Thank you, but I already tried. Now I found a way to solve the problem. I just created a new project and reimported my vhdl and sch files. The only thing I had to do is assign the pins again in Designer but everything was then ok. It took less time than continue to look after the mistake! Thank you for your help! See you next time on this group,

Marie

Reply to
Marie

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