Actel. Libero. Synplify

when I synthesize the FPGA (ProASIC PLUS) in Synplify of Libero I have got a lot of warnings: "Unbound component (DFF or AND2...) mapped to black box". It seems that don't recognize the basic components, =BFdo I need any library?

thanks

Reply to
dorama2
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(top posting due to bad quote)

If you're not using the FPGA primitives defined by the FPGA vendor which typically don't include DFF or AND2, you must include a library. Long ago Synplify required the unisims.v file for the Xilinx devices I worked with was added to the project. Thay have since changed the tool to imply the library directly from the use of the device.

Check what your FPGA supports to figure out what primitives are supported by the chip. Since Actel isn't as mainstream as Altera and Xilinx, there may still be a need to manually attach the library to your project.

- John_H

thanks

Reply to
John_H

thanks

Maybe not. The placement tool may recognise the names of the black boxes in the synthesis results as primitives and insert the appropriate parts. Try a place and route and see what happens! Cheers, Syms.

Reply to
Symon

in

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On place and route everything is OK. But this question-warning worried me. I don=B4t find unisim.v for Actel.

thank again,

Reply to
merche

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