Actel Fusion FPGA

More details please :)

(I'm not overly-familiar with the ADC, but if you provide a few more details, either I or someone else may be able to help.)

K.

Hey, I am trying to configure the ADC for voltage monitoring part. I have to use only three channels, So I am using AV0, AV1 and AV2. I am using Flash running at 8MHz to initialize and 40MHz is the fast clock after initialization which I am using as analog system clock. In SMARTGEN in the analog system builder I am selecting "ADC Sample and Sequence Control only". And I am only outputting ADC Results from the analog system.

Te problem is that nothing comes out on the ADC Result. In the post layout simulation, I see that Flash initialization is done, but the ADC Channel and ADC Result is always zero along with ASSC_Done, ASSC_Wait, ChLAT, ChSAT signals.

Out from the Analog system Block here is the code I use to read out the ADC Results.

library ieee;

library fusion;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_signed.all;

entity strm_ebs is

port ( ebs_right,ebs_up,ebs_left,ebs_down : out std_logic; rssi0,rssi1,rssi2,rssi3,rssi4,rfa0,rfa1,rfa2,rfa3,rfa4, rfb0,rfb1,rfb2,rfb3,rfb4 : out std_logic_vector (11 downto

0); adc_result : in std_logic_vector (11 downto 0); adc_ch : in std_logic_vector (4 downto 0); --adc channel adc_data_valid,clk_5k,reset : in std_logic );

end strm_ebs;

architecture arch_strm_ebs of strm_ebs is

begin

---------Generating ebs signals -------------------

Process (clk_5k,reset) variable ebs_sig : std_logic_vector (3 downto 0) :=3D "0000"; begin

if reset=3D'0' then ebs_sig :=3D (others =3D> '0'); ebs_right

Hello all,

I am trying to configure the ADC for voltage monitoring part. I have to use only three channels, So I am using AV0, AV1 and AV2. I am using Flash running at 8MHz to initialize and 40MHz is the fast clock after initialization which I am using as analog system clock. In SMARTGEN in the analog system builder I am selecting "ADC Sample and Sequence Control only". And I am only outputting ADC Results from the analog system.

In the post layout simulation, I see that Flash initialization is done and I see ADC results as well as the three ADC Channels I am configuring in my design. So post Layout simulation gives me perfect result but the design does not give any result on DC Result in reality.

In my design, I have used a Dual Port RAM as well that comprises 128 addresses of 16 bit wide data. I am reading out the ADC Results on to the RAM memory but I see in POST LAYOUT Simulation perfect results but do not see anything when I download the design on the board.

The design meets maximum delay timing requirements as well in the timing analyzer.

Please help me if someone has suggestions.