Actel FPGA programming using libero 8.1 generated SVF files

Hi

Since version 8.1 Actel provides SVF programming file generation for A3 FPGA's but I have problems using those SVF files:

For first testing i used Xilinx IMPACT as SVF playback engine, and I got scan data mismatch error on any actel SVF files

then i used my own SVF player and got same result

(JTAG port and Actel FPGA connections are ok, my own software can identify chain ok)

when looking into the Actel tools generated SVF ==================================== FREQUENCY 4E6 HZ; STATE RESET; RUNTEST IDLE 5 TCK; ENDIR IRPAUSE; ENDDR DRPAUSE; SIR 8 TDI(0F); SDR 32 TDI(00000000); STATE IDLE; RUNTEST IDLE 1 TCK; SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); ====================================

that SVF set IR to IDCODE (0F) clocks out 32 bits without using return data then without shifting anything to IR will go again shiftDR and try read IDCODE

strange, while impact NEVER sees correct IDCODE readback, my own SVF player sometimes see the IDCODE returned on the second DR shift (never on first)

Antti