Actel FIFO in Synplify: blackbox is missing a user supplied timing model

I'm having problems with Synplify and the Actel macros.

As part of a project I'm using a FIFO generated by Libero's ACTgen to save processed data that I also output through the pins of the FPGA (an Actel APA300), for computer readback. ACTgen produces a VHDL file which instantiates the RAM/FIFO blocks (it creates two or more FIFO256x9SST, depending on FIFO depth) and provides an interface to make them act as one bigger FIFO, which I then instantiate in my code.

I synthesize it with Synplify (both normal and Pro have the same problem) 8.0A, which is specific for Actel, and then Place&Route with Actel Designer. The timing analyzer claims to meet the desired frequency of 40MHz. The program produces a STAPL file which I use to program the FPGA. When I test it, however, the FIFO malfunctions. The data is being processed correctly (because it comes out of the pins OK, I can check that with an oscilloscope) but when I read it back from the FIFO, some of the bits change. I know the readback interface works fine as well, and I have tried on two different FPGAs of the same model, so it must be the FIFO. When I use a very small FIFO, of depth 8 or so, everything works fine, but I need a longer depth (256,

512, or so). Everything points to a timing problem caused by the FIFO logic, since a change in only the FIFO depth causes it to work or not.

When I synthesize it with Synplify, it provides the following warning: @W: MT253 :"[mypath]\hdl\fifo_tc.vhd":234:3:234:4|Blackbox FIFO256x9SST is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) I searched, asked my friends, and investigated, and I found out that whenever an Actel macro is used, it gets mapped to a blackbox which, if there is timing information for it, Synplify uses to optimize paths. I also found that, when using my own custom blackboxes, I can use constraints to specify the propagation delay etc so that the synthesis uses it. I can now create a constraints file with the delays associated to the FIFO and the program will use them.

My problem, of course, is that I don't know whan values to use. I assume (perhaps wrongly) that Actel provides them in one of the libraries from either Libero or Synplify (they distribute the Actel edition of the program, so I assume they make the libraries) and I haven't found a way to include it. The other option is that they don't and I need to create the constraints file with the values which hopefully Actel provides (I don't know where I would get them, otherwise).

Can anybody offer any hints as to what I need to do in order to provide Synplify with the timing information?

Reply to
gadav111
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Hi,

just search online help for black box attributes: syn_black_box, syn_tsu, syn_tco, syn_tpd.

Online Help has appropriate information and also VHDL/Verilog examples.

Bye, Phil

Reply to
phil

syn_tco, syn_tpd.

Reply to
gadav111

ok, I see. If you don't know the timing numbers you have two choices:

  1. Check the datasheet. It should provide you with the desired information 2. If you don't have the datasheet you can run P&R and get the numbers from the timing report (but only if those paths are violated). If there is no violation there is no need to apply black box timing attributes any way. You could safely ignore Synplify's warnings.

Cheers, Phil

Reply to
phil

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