Actel Designer Warning: CMP201: Net drives no load

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Hi everyone,

I have several ports of my design that are not driving anything and left
'open' on purpose, using the 'open' keyword in my component
instantiation in vhdl.

Now I receive loads of 'Warning: CMP201...' from Designer because of
this. Is there a way not to be annoyed by these warnings with the
possibility to miss an important one?

I did not post this thread to comp.lang.vhdl because I do believe this
is not a vhdl issue but rather a tool issue.

Thanks a lot,

Al

--  
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
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Re: Actel Designer Warning: CMP201: Net drives no load

(snip)

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I think last time I did this (in verilog) I wired them as outputs
with the output enable tied low.  

Some time ago, the tools I used wired unused outputs low, and
it turned out that they were connected to other signals on the
board (that I didn't know about).

-- glen

Re: Actel Designer Warning: CMP201: Net drives no load
Hi Glen,

On 27/08/2013 20:22, glen herrmannsfeldt wrote:
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maybe I misstated my problem. The 'ports' I was referring to are ports
of components (using vhdl terminology) and therefore are not connected
to any physical port. They mostly refer to unused ports of vendor's IPs
(like PLL, fifo, etc.).

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That's an 'interesting' feature! Could you provide the name of the tool?


Re: Actel Designer Warning: CMP201: Net drives no load
On 28/08/2013 11:06, alb wrote:
..
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Quartus used to connect unused pins to ground, not sure if this is still  
the case. After discovering this my scripts always started with:

set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED  
WITH WEAK PULL-UP"

Hans
www.ht-lab.com


Re: Actel Designer Warning: CMP201: Net drives no load

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It seems to be the input tri-stated with weak pull-up now, in Quartus
13.0. I think I've used a Quartus fairly recently though where it's
still output driving ground...

Re: Actel Designer Warning: CMP201: Net drives no load


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still output driving ground...  

Not true...Quartus allows you to specify unused pins as:  

As input tri-stated? The pins are reserved as tri-state input pins.
As output driving ground? The pins are reserved as output pins and drive  
the ground signal.
As output driving an unspecified signal? The pins are reserved as output  
pins and drive any signal.
As input tri-stated with bus-hold circuitry? The pins are reserved as tri
-state input pins with bus-hold circuitry.
As input tri-stated with weak pull-up? The pins are reserved as tri-state
 input pins with weak pull-up resistors.

http://quartushelp.altera.com/11.1/mergedProjects/comp/comp/comp_tab_dp_unu
sed_pins.htm

Re: Actel Designer Warning: CMP201: Net drives no load

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I don't understand. What part did you feel was not true? I merely
pointed out the default has been changed fairly recently. Oh, I guess
the default being implicit rather than explicit confused you?

Re: Actel Designer Warning: CMP201: Net drives no load
On Wednesday, September 4, 2013 7:50:15 AM UTC-7, Anssi Saari wrote:
 to connect unused pins to ground, not sure if this is >>> still the case.  
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t driving ground... > > Not true...Quartus allows you to specify unused pin
s as: I don't understand. What part did you feel was not true? I merely poi
nted out the default has been changed fairly recently. Oh, I guess the defa
ult being implicit rather than explicit confused you?

Sorry if my comment offended you, that was not my intention.  The post you  
wrote left me with the impression that the Quartus tools would only either  
connect unused pins to ground or tri-state them.  That is not true which is
 why I flagged it.  I went back and looked at HT-Lab's original post you cu
t/pasted and saw that he mentions that he starts out his Quartus runs defin
ing what the unused pins do- you lost that context by not copying it.  Afte
r going back and reading that post your comment makes more sense now.  Agai
n, it wasn't meant to offend you.

By the way, I do remember a version of Quartus, 5.X IIRC, that had a defaul
t setting of tieing unused pins to ground.  It caused some spectacular resu
lts on a board I was working on a decade or so ago.  Like HT-Lab I learned  
my lesson on that one.


Re: Actel Designer Warning: CMP201: Net drives no load
On 8/28/2013 3:06 AM, alb wrote:
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The Xilinx CPLD tools used to do this for unused input pins. The
following is from some really old code. I eventually created a dummy
net to 'use' the unused inputs so they wouldn't do odd things.

Quoting the code:

-- A note about the 'xilinx_sucks' net:
-- The fitter seems to believe that pins that are defined to be inputs
-- which have no logic connected to them internally may be used by the
-- CPLD for intermediate logic and as outputs!!!. Without this net,
-- CPLD will output a clock signal on the A0 input pin!!!

I think that later I found a switch that disabled this 'feature'.

I always wondered if that was some kind of ground-bounce reduction feature.

Rob.


Actel Designer Warning: CMP201: Net drives no load
Is there a difference between Libero SoC and Actel designer? I use SmartDesign and right-click on the pins and set attribute to unused.

--  
Svenn

Re: Actel Designer Warning: CMP201: Net drives no load
On Tuesday, August 27, 2013 5:34:46 AM UTC-7, alb wrote:
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ing and left 'open' on purpose, using the 'open' keyword in my component in
stantiation in vhdl. Now I receive loads of 'Warning: CMP201...' from Desig
ner because of this. Is there a way not to be annoyed by these warnings wit
h the possibility to miss an important one? I did not post this thread to c
omp.lang.vhdl because I do believe this is not a vhdl issue but rather a to
ol issue. Thanks a lot, Al -- A: Because it fouls the order in which people
 normally read text. Q: Why is top-posting such a bad thing? A: Top-posting
. Q: What is the most annoying thing on usenet and in e-mail?

Al,
Not sure what the issue is, this is just the tool warning you that you have
 unconnected output ports on instantiated components.  If you don't care th
en ignore them.  I find it hard to believe that this is the only warning yo
u are getting, why are you concerned about it?

If you need more comfort this is from the Actel Knowledgebase for compiler  
warnings: (http://www.actel.com/kb/article.aspx?id=SL1055 )
CODE:  CMP201  
Description: An output net is not driving any inputs and will be removed fr
om the design.  
Recommended Action: None required, unless the net should actually be drivin
g logic. If so, correct and re-import the netlist.  


Re: Actel Designer Warning: CMP201: Net drives no load
On Tuesday, August 27, 2013 5:34:46 AM UTC-7, alb wrote:
Quoted text here. Click to load it
ing and left 'open' on purpose, using the 'open' keyword in my component in
stantiation in vhdl. Now I receive loads of 'Warning: CMP201...' from Desig
ner because of this. Is there a way not to be annoyed by these warnings wit
h the possibility to miss an important one? I did not post this thread to c
omp.lang.vhdl because I do believe this is not a vhdl issue but rather a to
ol issue. Thanks a lot, Al -- A: Because it fouls the order in which people
 normally read text. Q: Why is top-posting such a bad thing? A: Top-posting
. Q: What is the most annoying thing on usenet and in e-mail?

OK I just reread this and noticed you just want a way to silence these warn
ings if I am reading correctly... nope I do not know how to silence specifi
c warnings with the Microsemi Designer.  You probably have to pull the text
 into python and do it there if you really need to.  I quickly looked throu
gh the literature I have on Actel and the only related thing I saw was to l
imit the total number of warnings shown.  The default is 10,000 but you can
 change it with the tcl command "-pdc_eco_max_warnings value" where value i
s the max number of warnings.  This is not going to fix your issue though.

Re: Actel Designer Warning: CMP201: Net drives no load
Hi Chris,

On 29/08/2013 02:29, Chris wrote:
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[]
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yes, you are reading correctly. Unfortunately warnings are not born all
equal and a design may have several of them, some can be ignored and
some should not. I simply would like to get rid of the ones I do not
care about.

nope I do not know how to
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IMO having a maximum number of warning is extremely risky. You may fall
in the situation where you may miss important ones.
On top of it I consider warnings an indication that something is not
going ok and I can live with a warning if and only if I know exactly why
is there. But I do not want to keep trace of zillions of warnings which
are meaningless.

Svenn suggested to use the 'unused' attribute in SmartGen, but SmartGen
is a just a macro generator and you would have to instantiate the
component in your vhdl anyhow and it is typically assigned to 'open'
(vhdl keyword). But this will flag a stupid warning in Designer.



Re: Actel Designer Warning: CMP201: Net drives no load
Another way to clear these warnings is to make a mux'ed set of signals goin
g to unused pins that you never select using an outside trigger.  For examp
le for ten signals that are giving you unconnected warnings and assuming yo
u have some spare IO make a test mux that is high impedance in the default  
setting and selects these unused signals in other settings that never actua
lly get selected.  You just need to fool the synthesis tool by making the s
elector an outside signal.  I have done this with a mux selector coming fro
m a mmi from a processor and it works.  You can probably do a -no prune dir
ective to save the mux too.  Kind of a pain but it would fix the problem if
 you have the spare IO.

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