Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables

I have a design that uses a 100Mhz system clock, but only a very small portion actually runs at 100MHz. The rest of the FFs in the design use a synchronous "clk_10M_en" signal which is active for one clock period and repeats every 100ns. I would like to know how to specify the constraints correctly so that Actel Designer (i.e. SmartTime)) knows "that paths FROM FFs using clk_10M_en TO FFs using clk_10M_en" are 100ns paths, not 10ns paths.

It's quiet easy to add a multicycle path constraint on the two registers, such as:

set_multicycle_path 10 -from {reg1:CLK} -to {reg2:CLK}

But what I need is a solution that can find these registers when they are buried in a hierarchy of modules. Since they all use clk_10M_en as their enable, there should be a way to perform a "find" and then set a multicycle path constraint between each regsiter.

I have contacted Actel but they refer me to their docs or using the GUI tools which does not solve my problem. Surely this can be done via the .sdc constraints file using some TCL code.

TIA.

David

Hi David,

You might be able to do it in your synthesis tool (in my case Precision). In one of my designs an FSM output stage drives the enable of some output registers. I can then use the Precision report_connection command to list all the CE pins this FSM output signal is connected to.

# COMMAND: report_connections -net state(4) # ix35.out {ix5.in[0]} reg_sin(11).ce reg_sin(10).ce reg_sin(9).ce reg_sin(8).ce reg_sin(7).ce reg_sin(6).ce reg_sin(5).ce reg_sin(4).ce reg_sin(3).ce reg_sin(2).ce reg_sin(1).ce reg_sin(0).ce reg_cos(11).ce reg_cos(10).ce reg_cos(9).ce reg_cos(8).ce reg_cos(7).ce reg_cos(6).ce reg_cos(5).ce reg_cos(4).ce reg_cos(3).ce reg_cos(2).ce reg_cos(1).ce reg_cos(0).ce

I can then use a bit of Tcl to filter this list and write out some MCP commands

set_multicycle_path -design rtl 4 -to reg_sin(*).in set_multicycle_path -design rtl 4 -to reg_cos(*).in

Which is then translated by Precision to an Actel flavoured technology SDC file before invoking designer,

set_multicycle_path 4 -to { U1/reg_y10_s(9)_pbrt_0:D reg_sin(3):D reg_sin(2):D reg_sin(4):D reg_sin(5):D reg_sin(6):D reg_sin(8):D reg_sin(1):D reg_sin(7):D U1/reg_y10_s(10)_pbrt_0:D U1/reg_y10_s(11)_pbrt_0:D U1/reg_b(1)_dup_1028_pbrt_0:D U1/reg_sin_addsub12_29_modgen_add_12_Carry(1)_pbrt_0:D U1/reg_sin_addsub12_29_modgen_add_12_pog_array(2)(4)_pbrt_0:D U1/reg_sin_addsub12_29_modgen_add_12_pog_array(2)(8)_pbrt_0:D U1/reg_sin_addsub12_29_modgen_add_12_pog_array(2)(8)_pbrt_0_dup_52374:D U1/reg_sin_addsub12_29_modgen_add_12_g_array(2)(4)_pbrt_0:D .. snip continue for another 2 pages...

You might be able to do the same using the standard SDC get_pins()/get_nets()/get_cells/etc commands but I haven't tried it,

Hans

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