Accessing one SDRAM from two MicroBlazes

I assume you are implementing the two Microblaze devices within a single FPGA, in which case it becomes a simple matter of a separate memory interface and an internal bus arbiter of some description.

Although you say one Microblaze is responsible for communication to external interfaces, there's no reason you can't have a bus mastering scheme provided the data rate is not too high (hint: use internal buffers).

Another alternative is a dualported RAM (so you would have an interface from EACH microblaze), but these don't usually come in the sort of size you need, to say nothing of the synchronisation issues to be resolved..

As to the memory type

What is the data rate to memory required? Average? Burst?

What power consumption can you live with?

Do you have a SDRAM controller core? Or do you intend to write one? Can you live with the logic it will take? or DDR? (although that seems way over the top for 3MByte of data).

There are a number of solutions, but it's hard to answer without knowing these things; These questions are fundamental to choosing the memory type you should use.

Cheers

PeteS

Try mch_opb_[sdram|ddr] controllers that come with EDK. You should be able to connect two MB's directly to memory and an OPB channel for peripheral accesses to memory.

/S

Hello Siva,

Do you mean connect all two MB and sdram controller to one OPB bus? Is it possible without arbitrator or you mean something else. I am working on a similar project and thinking of making an arbitrator myself. Thanks for your information.

Wayne

MicroBlaze version 3 and above allow a direct connection from the I & D caches to memory. This channel is called XCL. This provides better performance since the protocol over this channel is optimized for cache accesses (cacheline bursts & target word first). The memory controllers that have this XCL interface are called mch memory controllers - mch_sdram/emc/ddr.

So your configuration would like this:

MB1 - i-XCL and d-XCL connected to channels 0 & 1 of mch_sdram MB2 - i-XCL and d-XCL connected to channels 2 & 3 of mch_sdram OPB and opb peripherals connected to OPB channel (4) of mch_sdram.

The arbitration between the 5 ports (4 XCL, 1 OPB) is done inside the memory controller, so you wouldn't have to write any arbitration logic.

In case you want to attach many many more masters to the OPB, even then you wouldn't have to write any arbitration logic, since it is included in the OPB logic itself.

/Siva

Hi Siva,

Thank you for your information. The MultiCHannel controller is eally an interesting design and good news for me.

For OPB, I ever tried to connect to Microblaze to one OPB bus but it didn't work. After I disabled one Microblaze it works. Could you suggest what's wrong with my design. Thanks for your help.

Sunwei

For

You might want to try using the newest tools, and enable dynamic priority on the OPB (C_DYNAM_PRIORITY).

/Siva

I see. Thanks Siva.

Okay, thanks a lot for your answer,

I'll check the details !

Bye BEN

PeteS schrieb: