Hi Guys,
I'm having a custom type in VHDL:
type alu_op_code is ( ALU_OP_IDLE, ... );
Now having a testbench written in TCL i wawnt to force signals of type alu_op_code.
How to actually do that? For std_logic data this is possible usng:
force signal_name '0'
But how to use that with custom types?
Thank you in advance! Cheers Robert