Accesing a procedure

Hi,

I have a problem with accessing a procedure in a special manner:

Some background information: I want to use a testbench in which I write the valid input data (16bit) for my VHDL module under test into a ringbuffer. That is my VHDL module gives out data (16 cleaned bit) after some pipelining stages. These output data should be compared with the data I have written into my ringbuffer (The data in the ringbuffer are unstuffed, that is after six consecutive ones the following zero is unstuffed. This unstuffing function is of course also implemented in the VHDL module under test itself.). By the means of this object-oriented check I want to verify my module.

Here is my problem:

------------------------------------------------------------ architecture testb of xy is signal t_Enable_in : std_logic; signal t_Clk : std_logic; signal t_Reset : std_logic; signal t_In_data : std_logic_vector(15 downto 0); constant history_size : integer := 1024; signal t_history : std_logic_vector(history_size-1 downto 0);

... procedure feed(signal d : in std_logic; signal history : out std_logic_vector(history_size-1 downto 0)) is variable ptr : integer range 0 to 1023; variable n : integer range 0 to 6; begin

if ((n=6) and (d='0')) then null; --??? Does this exist in VHDL ? else history (ptr mod history_size) t_history ); end loop; end if; end if; end process;

-------------------------------------------------------

------------------------------------------------------- end testb;

I get the following error message (Modelsim5.7e)

# ** Error: H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/simulation/modelsim/tb_decode_destuff_hs.vhd(134): The actual for parameter d must denote a static signal name. # ** Error: H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/simulation/modelsim/tb_decode_destuff_hs.vhd(146): VHDL Compiler exiting

How can I change that?

I would appreciate your time and help.

Kind regards Andres V.