hello all, I just want to test my new HDL model it passed the simulation testings. but unfortunately my fpga board is damaged and is in repair stage. Can id do the the timing test with the netlist file. I am proceeding in the following way.
is this method is correct or industry standarad ??? requesting your comments on this. regards sumesh
Butt now i am finding difficulties in simulating the netlist. Model sim is reporting errors that a synthesized component XORCY is not in the library. I tried to import the unisims libray but it did not helped. what could be the problem. Please help.... regrds Sumesh
I found some verilog code for the XORXY etc. But for one component OBUF there is a line "GTS = glbl.GTS;" whats this means and model sim XE version is giving "unresolved symbol" while loading the design. How can i avoid the error?? regards Sumesh
Hi Sumesh,
As you load your design, make sure you compile also the module called glbl.v (it's located in the xilinx libraries). And when you load the design, load your top module along with glbl module.
Vladislav
thanks Vladislav.. it worked perfectly... can i substitute this process for the real fpga.... what is the effect of routing delays compared to the component delays.... how can i account for that in the simulation environment...
Sumesh
Sumesh,
You have asked a very good question., quite a few people really ask it. It depends on several factors, such as the speed of the design, percentage of used resources and more... I have met 30% / 70% logic / routing delay distribution, as well as 70% /
30%.Do not account this into your simulation environment, because the best simulation you could find is the board with FPGA Unless you are designing ASIC.......
Vin that case is there any better procedure/tool with which i can analyse timing issues better than simulation. Please suggest any books/materials on this topic. I agree that the real silicon is the best model. But how can we analyse it if there is some problem in the timings ??? Thanks for your advice Sumesh V S
Dear Sumesh,
Sorry for late reply. The best I can offer you is as following : Never use timing issues in simulation. Use simulation only for functional verification of your design. As a post-synthesis process, always use Timing Analyzer. If your design has a very high speed, simply pipeline it as much as possible.
There are some books on digital design, which may give you the idea of quantisizing the combinational logic by number of its level, but in my humble opinion, nothing substitutes the real experience and this is why all of us are in this newsgroup, to offer our help to everybody else...
Vladislav
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