ABEL to VHDL translate

Hi all,

can someone help me to translate following ABEL code to VHDL on Xilinx.

-- BOOT pin istype "reg_d";

-- !IOWR pin;

-- BOOT.clk = !IOWR;

-- BOOT.aset = RESET;

-- BOOT.aclr = 0;

-- BOOT.d = IOD0 & BOOT_BASE # (BOOT.pin & !BOOT_BASE);

-- BOOT.oe = 1;

It seems to be a clocked process, but IOWR is not a real clock, it changes only sometime. The .pin according to ABEL language is a feedback, so should I define it with a temp signal associated to BOOT pin like:

signal boot_tmp: std_logic;

boot_temp