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A Typical Design Cycle

Dear all; Please tell me if I'm wrong. A typical design cycle for FPGA is to use the IEEE and Unisim libraries and their primitives (if you wish) and run the functional simulation with Modelsim and after that you go for some synthesis tool like LeonardoSpectrum or Precision RTL. Am I right?

ps. I know, that in case you don't want to sue the primitives as IPs in your design, the synthesis tool will extract them automatically if you restrict yourself to some kind of standard templates.

I know that I might be missing a lot. Give me directions please.

Thank you..

ps. in what way can I use SIMPRIM library?

Reply to
Mohamed Elnamaky
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Hi,

FPGA design cycle looks as below: -Requirement gathering -Architecture and high level design -Low level Design -RTL Coding (Can include Xilinx primitives like block RAM, FIFO - coregen module) -RTL simulation -Synthesis & place and route -Bit file generation and Bit downloading

To answer you question on SIMPRIM; Since a portion of RTL contains primitives from Xilinx / any FPGA vendors, we need some behaviroual model for RTL simulation. thats what SIMPRIMS - SIMulation PRIMitiveS During synthesis, we will be adding the FPGA library which has gate implemenetaion of these primives.

Regards, Muthu

Reply to
Muthu

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