A "simple" problem...

Good morning, I'm a beginner with FPGA. I've recently built a simple board with one Spartan 3 FPGA, no configuration PROM (I haven't it now), a power supply, and a JTAG connector. I've connected the FPGA for use only the JPAG port (M0-M1-M2=1-0-1). But when I start iMPACT for configure the FPGA, it see an "UNKNOWN" device. And if I try to get the device ID I get this error.

Validating chain... Boundary-scan chain validated successfully. ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '1': Device IDCODE : 00000000000000000000100000000011 INFO:iMPACT:1579 - '1': Expected IDCODE: 00000001010000001101000010010011

I've checked the circuit and the connections, but all seems to be ok. Is this a common problem? What can be wrong???

Another question : if I put the device in JTAG configuration mode, how I must connect PROG_B and INIT_B? I think the first one must be connected to GND, and the other to +2.5V through a pull-up is it right?

Thanks.

Enzo

Reply to
Enzo B.
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"Enzo B." schrieb im Newsbeitrag news:efQ4e.742956$ snipped-for-privacy@news3.tin.it...

device.

1 the M0,M1,M2 no need to connect at all, the JTAG is enabled anyway 2 PROG_B doesnt matter as long as you try to identify the chain, however configuration over JTAG may fail if there is no pullup on PROG_B 3 INIT_B pullup

everything else doesnt matter if you have xilinx cable III or IV then you can use

formatting link

to see if that application can detect the jtag correctly

and there is JTAG chain debugger in the impact

antti

Reply to
Antti Lukats

Hi, thank you for your message.

Ok, I've also read this in the datasheet.

I have a pullup on PROG_B and another on INIT_B, but have seen that if I connect PROG_B to GND I can read 0x803 as device ID on iMPACT. Instead, if I connect the pullup on PROG_B, the device ID readed was all zeros.

I've downloaded your program, it see the Xilinx Cable III and a device "1:FC000803" (is this the device ID readed ?).

Any idea?!?

Thank you again for the response.

Enzo

Reply to
Enzo B.

"Enzo B." schrieb im Newsbeitrag news:oJV4e.1185199$ snipped-for-privacy@news4.tin.it...

I

the value of PROG_B should not matter for the JTAG to be operational, something is really funky if it has any influence on the ID readback

yes that is the 32 bit IDCODE as read back from the device, before the IDCODE my program validates the number of devices in the chain what is sensed correctly to the chain isnt completly broken

hm have you powered VCCAUX with 2.5 and do have VCCIO on the banks that contain the JTAG pins ?

when I did a wire wrap proto with Virtex-2000 in BGA then my mistake was that I did not power the VCCIO in the JTAG banks, and second was the missing pullup on PROG_B

antti

Reply to
Antti Lukats

I've checked and re-checked the chain (it's only 4 connections!!) with a multimeter, but it appear ok. I've also used the debugger in iMPACT for verify the correct value of the voltage on TDI-TDO-TMS-TCK, and all seems to be ok. This is a strange problem.

I've powered the four (my FPGA is in TQFP144) VCCAUX with a stable 2.5V, the four VCCINT with a stable 1.2V, and the twelve VCCO all with 3.3V. I've read the XAPP453, on page 13 there is a simple schematic for JTAG configurations, my schematic is similar but with only one FPGA and with a pullup (to the 2.5V) on PROG_B. Until now, I've tried various combinations of M0-M1-M2, HSWAP_EN, PROG_B, INIT_B signals, but with the same poor result : iMPACT (and also your frequency-meter) detects one device, but doesn't read the ID correctly.

!!! I'm doing my board with wire wrap... I have problems with "only" an XC3S50, I can't imagine what can be a Virtex in BGA ! But if you tell me this, I suppose the capacitors on the power pins of the FPGA aren't critical, is this right? On my board, now, I haven't connected a capacitor between *each* power pin and GND... can be this the cause of my problem???

Thank you for the help.

Enzo

Reply to
Enzo B.

"Enzo B." schrieb im Newsbeitrag news:nT95e.747333$ snipped-for-privacy@news3.tin.it...

to

the

XC3S50,

a

no caps on *each* pins are not so critical at all.

hm the JTAG cable, that could be a problem, if it is self made have you used the same JTAG cable with any other FPGA?

I have build quite a many cables, and there are problems sometimes. it can even happen that 5 wires to LPT port works better than Xilinx original cable IV

possible the TDO out from FPGA is not enough voltage or something

as it looks like the FPGA is ok as of connections then I would suspect the download cable as next..

antti

Reply to
Antti Lukats

Hi Antti,

yes the cable is self-made, and with this I've programmed some CPLDs but never an FPGA.

I've experimentally seen that it works down to 3.7V connected to an XC9572 (the only CPLD I have here at home!). I suppose the cable also works correctly at lower voltages, since the two

74HC125 runs down to 2V. Currently I can't see the signals with an oscilloscope, but have tried to read the ID with a 3.3V powered buffer connected between TDO of the FPGA and the programmer, but have obtained the same result.

At this point, I have only two things:

1) buy a 3.3V CPLD and re-test the cable (is this a realiable test?) 2) try the cable on another PC (I know that sometimes the parallel port can give problems).

I'll tell you if I'll discover the problem...

Thank you again.

Enzo

Reply to
Enzo B.

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