A problem about GAL26V12

I have a very simple design that should fit in a GAL26V12 with ease, but I keep getting "Design does NOT fit" What's going on? ABEL Example: MODULE Test1 CSN pin; K4,K2,K0,K6,K1,K5,K3,K7 pin; K = [K0,K1,K2,K3,K4,K5,K6,K7];

D7,D6,D5,D4,D3,D2,D1,D0 pin; D = [D0,D1,D2,D3,D4,D5,D6,D7]; Equations D = K; K.oe = !CSN; END

This won't fit. and give me as follows messages.

---Device 'p26cv12' ---Note 4042: Unable to assign D4, need more pins ---like pin 27. ---Note 4042: Unable to assign D5, need more pins ---like pin 27. ---Note 4042: Unable to assign D6, need more pins ---like pin 27. ---Note 4042: Unable to assign D7, need more pins ---like pin 27. ---Note 4042: Unable to assign D4, need more pins ---like pin 23. ---Note 4042: Unable to assign D5, need more pins ---like pin 23. ---Note 4042: Unable to assign D6, need more pins ---like pin 23. ---Note 4042: Unable to assign D7, need more pins ---like pin 23. ---Note 4042: Unable to assign D4, need more pins ---like pin 22. ---Note 4042: Unable to assign D5, need more pins ---like pin 22. ---Note 4042: Unable to assign D6, need more pins ---like pin 22. ---Note 4042: Unable to assign D7, need more pins ---like pin 22. ---Design does NOT fit

---Done: failed with exit code: 0001.

        Best regards!        
Reply to
Li GenZhu
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I have a very simple design that should fit in a GAL26V12 with ease, but I keep getting "Design does NOT fit" What's going on? ABEL Example: MODULE Test1 CSN pin; K4,K2,K0,K6,K1,K5,K3,K7 pin; K = [K0,K1,K2,K3,K4,K5,K6,K7];

D7,D6,D5,D4,D3,D2,D1,D0 pin; D = [D0,D1,D2,D3,D4,D5,D6,D7]; Equations D = K; K.oe = !CSN; END

This won't fit. and give me as follows messages.

---Device 'p26cv12' ---Note 4042: Unable to assign D4, need more pins ---like pin 27. ---Note 4042: Unable to assign D5, need more pins ---like pin 27. ---Note 4042: Unable to assign D6, need more pins ---like pin 27. ---Note 4042: Unable to assign D7, need more pins ---like pin 27. ---Note 4042: Unable to assign D4, need more pins ---like pin 23. ---Note 4042: Unable to assign D5, need more pins ---like pin 23. ---Note 4042: Unable to assign D6, need more pins ---like pin 23. ---Note 4042: Unable to assign D7, need more pins ---like pin 23. ---Note 4042: Unable to assign D4, need more pins ---like pin 22. ---Note 4042: Unable to assign D5, need more pins ---like pin 22. ---Note 4042: Unable to assign D6, need more pins ---like pin 22. ---Note 4042: Unable to assign D7, need more pins ---like pin 22. ---Design does NOT fit

---Done: failed with exit code: 0001.

Reply to
Li GenZhu

It looks like it's assigned the I/O pins first, and has assigned them all to the K bus. Thus when it tries to associate the D bus (output) with an output pin it doesn't have any available (all the remaining pins are input only) Perhaps if you just swap the placement of the K and D definitions, so that D is before K the compilation (and placement) will succeed. For what you're using the device for it seems wasteful to use a PLD, why not just use a tristate buffer??

Reply to
Bevan Weiss

to

D

Hmm something else I didn't pick up on earlier... If K is your input to the buffer, why are you changing it's output enable state?? If you want K to be the output, then your assignment statement should surely read K = D, as opposed to D = K.

Reply to
Bevan Weiss

thank all kind friends. Now it is ok, as you say, D is output, so it ought to be D.oe = !CSN. thanks a lot.

Reply to
Li GenZhu

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