a newbie question

STA - static timing analysis, what's so "static" about it that people could it "static" as if there is such thing as "dynamic" timing analysis which I haven't hear of. Please enlight.

Thanks, Charles

Reply to
charles
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"dynamic" timing analysis is timing anaylsis performed by running a gate-level simulation annotated with timing information. The problem with this, is that only logic changes that occur in the simulation have their timing verified. With STA, all paths/state changes are covered, without the need to test-vectors.

Cheers, JonB

Reply to
Jon Beniston

But my understanding is that you will always need stimulus or test vectors to simulate your design to see if they are functionally correct. So I guess what you mean by STA not needing test vectors is that the static timing analyzer will check all the paths in the design to find the paths with longest delay to determine the maximum operating frequency. It will even go thru the paths/logics that are not covered by the test vectors. So I guess the sole purpose of STA is to determine longest delay paths, so as to give the designer ideas where and what to constraint to improve the clock frequency. And I guess, during this interative constraint/synthesis/STA cycles, some constraints might be incoherent, thus causing the situation where the constraint is met but functionally broken.

So is it fair to say that: "dynamic" timing analysis:

  1. It's part of gate-level simulation.
  2. If the gate-level simulation (with all the delays,i.e., logic plus routing, accounted for) passes the functional test with all the available test vectors, we can say that we have archieve timing closure;
  3. Timing closure is only as good as your test vectors. If you don't have
100% coverage of your logic/states, you always run a risk of timing failure in untest circuit.

Static Timing Analysis:

  1. Examine all paths and states to find the longest delay path to calculate the maximum frequency. Designer uses this information to specify the constraint to improve the frequency, or use techniques such as register rebalancing or insert an extra FF.
  2. It is done without any testvectors, so it is done by the tool automatically in both post map and post place&route. It does not concern itself with the functionality of circuit.
  3. It seems that you have to functionally understand the circuit before someone can specify some coherent constraints. So I guess constraints are usually specified by the RTL designers themselves. So what does the back-end process usually invovles with then?

Please comment, and thanks so much for your time!

Reply to
charles

It's simple, the pioneer Synopsys defined that term...I guess that's intended to differentiate itself from gate-level simulation...

When you are the pioneer in a field, you can define funny terms too...

Kelvin

guess

go

guess

failure

calculate

Reply to
kelvin_xq

Yes, consider writing an hdl testbench to provide the stimulus for your functional verification.

It has nothing to do with test vectors. It's an automated test of the maximum delay from Q to D between each register.

It is to prove that the design will run without timing problems at the required frequency. This assumes a 100% synchronous design.

Consider using simulation code coverage to make sure the functional sim is complete.

No. You have done an incomplete and perhaps unnecessary double check on the static timing analysis. Timing closure means doing whatever is necessary to meet the fmax you need in static timing.

No. A functional test is only as good as your code coverage.

-- Mike Treseler

Reply to
Mike Treseler

Thanks Mike. I kindly of understand it now. But what is the best way to handle clock domain crossing where you need to synchronize between the two domains. And I guess the clock domain part circuit really needs to be tested with gate level simulation with the sdf back annotation, right? I mean that is not part of synchronous design.

Reply to
charles

Hi Charles, I often use a circuit posted by 'Rickman'. Go to Google groups advanced search

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and search for the phrase "simple sync circuit" in comp.arch.fpga. Another favourite of mine is Xilinx's 'self addressing fifo' design too. Find it in XAPP291 on their website. Good luck, Syms.

Reply to
Symon

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No. See:

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You are welcome. -- Mike Treseler

Reply to
Mike Treseler

For synchronous design all FFs clock together, so static timing tells just about all you need to know. Tools are designed for synchronous logic, and people design using synchronous logic because that is what the tools do.

If you have multiple clock domains, gated clocks, or otherwise not all FF's have the same clock then you need to do timing analysis that takes that into account.

There is also dynamic logic, similar to DRAM where data is stored on capacitors. Many early Intel processors used dynamic logic, where the minimum clock frequency was 2MHz or so. Possibly that is the origin of the static/dynamic timing analysis.

-- glen

Reply to
glen herrmannsfeldt

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