A new domain for FPGAs ? Function approximation

Hi, I don't know, what is state-of-the-art for function approximation on FPGAs.

I developed this :

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"Paper" (10 minutes hack) for this :

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If I tried to implement the constructor for PBFs in VHDL, like a Float-Core-Generator, would I need to generate VHDL code, or can VHDL function generate intermediate gates ?

If I tried to implement the solve() procedure, I would need a random number generator. Is there a Xilinx IP core for this ?

BTW: I am using a Spartan3

I will extend my website and implement the generator in JavaScript.

Best wishes Thorsten Kiefer

Reply to
Thorsten Kiefer
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Yes, VHDL functions can imply combinatorial logic.

Andy

Reply to
jonesandy

But it is not possible to create a whole entity, right ? For a whole entity I need an intermediate VDHL file, right ?

Reply to
Thorsten Kiefer

I am not so sure what you are asking. In CS terms, VHDL is a compiled language, so you can't read in expressions and then execute them as VHDL code.

Well, actually I am not sure that you can't in simulation, but you can't when using it for logic synthesis, which is what you do when working with FPGAs.

More generally, though, some FPGAs allow partial reconfiguration which is the logic equivalent of dynamic linking.

About 10 years ago, I know about someone who had an FPGA with built-in PowerPC cores, running linux on one, and then generating logic on that processor, and loading it into the FPGA.

If you want more detail, you have to be more specific about what you want to do, and why you want to do it. (The reason can be a school project, but the answer will be different.)

The usual reason for doing something in an FPGA instead of software is that you need to do it much faster, and/or (usually and) zillions of times. (Millions or billions can still usually be done better in software.)

One problem that I know of, and an interested in doing in an FPGA, has a fairly simple operation that it does 1e19 times, every few days.

Now, since the primary logic element of most FPGAs is a small RAM (look-up table), you can just configure some and load whatever values you want to load into them. (But with fixed routing.)

Many software random number generators should be easy to implement in hardware, and for many more bits than the software versions.

-- glen

Reply to
glen herrmannsfeldt

Yes, the top-level module for a synthesis job is always an entity and it's architecture. The architecture could call the function concurrently, or use an explicit process (clocked or combinatorial) to call the function.

The function can be declared in a package ("used" by the entity/architecture), or in the architecture itself.

Andy

Reply to
jonesandy

Thanks a lot for all your help ! I will try this as soon as I have an open source / free VHDL simulator environment.

Thorsten

Reply to
Thorsten Kiefer

There are lots of free simulators. Each FPGA vendor has a free set of tools which includes a free simulator. If you want an open source VHDL simulator, your options are much more limited. GHDL is the only one I am aware of off the top of my head, but a search turned up this page which lists some other possibilities.

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Rick
Reply to
rickman

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