A difference between VHDL sources working

Hi

Can someone tell me if there is a defference between the following two VHDL sources working:

  1. process begin wait until C'event and C='1'; if B='0' then Q
Reply to
toomuch
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It's apparent from the code: Case 1 says "wait for clock, THEN test B and act accordingly" Case 2 says "Test B, decide how to act, THEN wait for clock"

Also, Case A is synthesisable (be :Hi : :Can someone tell me if there is a defference between the following two VHDL :sources working: :1. :process :begin : wait until C'event and C='1'; : if B='0' then : Q

Reply to
David R Brooks

Yes.

Yes.

1 samples B and A just after the rising edge of C.

2 samples B and A just after the rising edge of C, but doesn't use the value of B until after the next rising edge of C.

2 is not good coding style. Don't have more than one wait statement in a synthesisable process.

Yes. Try: The VHDL LRM. Any VHDL text book. Any VHDL lecture notes. The VHDL FAQ. Google.

Regards, Allan.

Reply to
Allan Herriman

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