A constant value of 0 in block

I have trouble during "Low Level Synthesis" of my code. It gets me following warings:

WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .

WARNING:Xst:1294 - Latch is equivalent to a wire in block . ... ....(from to ) WARNING:Xst:1294 - Latch is equivalent to a wire in block .

WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . ... ...(from to ) WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . ... ...(from to ) WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .

mostly are having a constant value of 0 in block .

The program is target in a Spartan3 starter board to read and/or write

8 addresses after the incoming address(currentX, currentY) chanages. Although it isn't follow the coding examples, it setup as a state machine.

================= Here is the code: =================

entity memoryCtr is Port ( direction : in std_logic_vector(2 downto 0); currentX : in std_logic_vector(7 downto 0); currentY : in std_logic_vector(7 downto 0); reset : in std_logic; enable : in std_logic; ready : out std_logic; action : in std_logic_vector(1 downto 0);

front : out std_logic_vector(15 downto 0); fright : out std_logic_vector(15 downto 0); right : out std_logic_vector(15 downto 0); bright : out std_logic_vector(15 downto 0); back : out std_logic_vector(15 downto 0); bleft : out std_logic_vector(15 downto 0); left : out std_logic_vector(15 downto 0); fleft : out std_logic_vector(15 downto 0);

clk : in std_logic; sramIO1 : inout std_logic_vector(15 downto 0); sramCE1 : out std_logic; sramUB1 : out std_logic; sramLB1 : out std_logic; --sramIO2 : inout std_logic_vector(15 downto 0); sramAddr : out std_logic_vector(17 downto 0); --sramCE2 : out std_logic; --sramUB2 : out std_logic; --sramLB2 : out std_logic; sramWE : out std_logic; sramOE : out std_logic ); end memoryCtr;

architecture Behavioral of memoryCtr is constant mapSize: integer := 256; -- 128*128 constant memSize: integer := mapSize/2; -- memSize -> 0 ->

memSize type memDatas is array (8 downto 0) of std_logic_vector(17 downto 0);

-- the value for memory location type state_type is (init, setup, read, write, outEnable); signal state: state_type := init; begin

memLoop: process(clk) variable addr :integer; variable readyEnable: std_logic := '1'; variable X, Y :integer; variable prevAction : std_logic_vector(1 downto 0) := "00"; variable tempData1, tempData2 : std_logic_vector(15 downto 0) := x"0000"; variable FmemData, FRmemData, RmemData, BRmemData, BmemData, BLmemData, LmemData, FLmemData : std_logic_vector(15 downto 0); variable memData: memDatas; -- the location for 8 memories variable dir : integer := 8; -- direction counter

begin ---------------------------------------------------------------------------------------- ----------state 1: accept calls and initialize the calls for current location ---------- ----------------------------------------------------------------------------------------

if reset = '1' then state

Reply to
YiQi
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The following warning is issued:

"WARNING:Xst:1294 - Latch is equivalent to a wire in block ."

Solution 1: This problem is fixed in the latest 5.1i Service Pack, available at:

formatting link
The first service pack containing the fix is 5.1i Service Pack 1.

Above message from Xilinx's web site, But I am using 7.1i already, it isn't that my errors should be fixed?

Reply to
YiQi

Try fitting your code into a template like this

begin if reset = '1' then init_regs; elsif rising_edge(clock) then update_regs; end if; update_ports; end process sync_template;

-- Mike Treseler

It is not in the stars to hold our destiny but in ourselves. -William Shakespeare

Reply to
Mike Treseler

Thanks William, For such a big program, it is very hard to follow 100% of the template. My code is already in that structure, except that it doesn't have to work in rising_edge(clock) for the else part.

One thing I really want to ask is does "equivalent to a wire in block" warning seriously important on synthesis? Is it saft to ignore that?

What I am more worry is the " a constant value" warning, I think I have to fix that as it may totally check my code.

Reply to
YiQi

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