Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Help to SImulate Uart TX
I'm using the following code. I've managed to make it work on my fpga before. but when I try to simulate on my modelsim, it seems that it never gets into the statemachine. I've configured the settings...
7
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15 years ago
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7 | |
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QPSK SymbolRate generator ...
I have built a QPSK modulator, but I have some doubts about the generation of SymbolRate variable. The SymbolRate range should from 1 to 45 Msymb/s. I intend to use an external AD9850 DDS, which...
7
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15 years ago
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7 | |
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basic chipscope pro query
Hello, I am new to chipscope pro.i read lot of documents but unable to get exact information.i worked with counter example which works fine now i implement a design of ram using VHDL,where i first...
4
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15 years ago
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4 | |
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ISE Simulator
Xilinx ISE 9.2 and 10.1 (Webpack) signal cntr: integer range 0 to 3; ... if(clk'event and clk='1') then cntr
4
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15 years ago
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4 | |
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synthesis warning
Hi, during synthesis I get many warnings. One of them is : WARNING:Xst:2404 - FFs/Latches (without init value) have a constant value of 0 in block . is connected to the input port of a subcell. Is the...
2
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15 years ago
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2 | |
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Xilinx ISE speed files compatibility
Does anyone know if I can copy a speed file from ISE10.1 to ISE8.2? They are of very much different size, which seems to say they are not compatible, but I thought I would ask anyways... I suspect...
4
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15 years ago
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4 | |
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Xilinx 10.1 service-pack error: ./setup: line 41: 1472 Segmentation fault
On my Centos 5.2 (x86 32-bit) Linux box, I've noticed a problem with the 10.1 service-packs. If I unzip to a directory called "/tmp/x/", then try to run ./setup, the installer gives me this...
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15 years ago
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HELP! How do I install Xilinx ISE WebPack?
I'm using Damn Small Linux version 3.4.8. I downloaded the file 10.1_Webinstall.zip to my hard drive. When I open this file, I get taken to /ramdisk/tmp/.emelfm-unpack . I open a shell and go to this...
1
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15 years ago
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1 | |
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Serial Pheripheral Interface for XILINX FPGA
Hi, I have one question if anyone can give me some clues. I need to realize SPI (Serial Pheriferal Interface for my project). Does anybody knows is there any free version of this core that can be foud...
5
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15 years ago
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5 | |
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Single ended interface at 70Mhz for FPGAs
hi, I am looking for connecting my proprietary 8 bit bus interface across two Xilinx FPGAs across the back plane, (10 inch trace). I dont want to use differential as that would take lot of pins, Is...
6
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15 years ago
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6 | |
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Free Webinars on PMP Certification Awareness and Roadmap
Dear Freinds I came across a website which conducts Free Webinars on PMP Certification (Project Management Institute, USA) Awareness and The Roadmap. It proved to be quite useful. This Training...
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15 years ago
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FiFo Help Needed
Can anyone help me check my codes? I implemented it, but when I run on Modelsim, there doesnt seem to be any data coming out of my FIFO during the clock cycles... my source is at
9
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15 years ago
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9 | |
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Effect of reheating and reballing on reliability of Xilinx chips
Hi Ausitn & Peter and whoever else from Xilinx is listening, I need your opinion on how number of reheating cycles with or without reballing, provided the rework is done professionally using proper...
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15 years ago
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Xilinx XPS and Multiple Microblaze
Hi, I know that it is possible to put multiple microblaze in a virtexIIPro. I am trying to design one architecture with two microblaze and two bram. When I try to generate Addresses, xps returns error...
2
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15 years ago
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2 | |
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External Clock Generator
Hi I wanna use an external function generator to feed the FPGA with the clock signal. I have come across a function generator from TTi (TG330). So I am wondering if this device is suitable to generate...
3
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15 years ago
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