Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Regarding Xilinx tool
My name is vignesh. I am also new guy to Xilinx .. i want to know the following things... please help me... 1. how can i create the *.ucf file using xilinx Tool ? (if you have provide me ) 2. how can...
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Configure registers of CMOS Sensor by Spartan3
Hi, I am trying to configure the registers on the MT9T001 Image sensor using a Spartan3 board. I fed a 50MHz to the SCLK, the SDATA is pull-up by 3.3V, and after feeding the start bit and 16bit...
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Can I store the output of my FPGA logic inside FPGA memory for debug data values?
Hi, I am using altera FPGA. How can I put the output of my logic into the FPGA internal memories(assuming I have unused memories available)?
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Help Needed - LPC Bus Interface
I've problem with my codes. I'm trying to make a LPC Bus interface with my Spartan 3E to tap the bus traffic coming from keypresses. I'm using the LCLK from the bus and the FPGA 50Mhz clock for my...
 
Help =(
I've problem with my codes. I'm trying to make a LPC Bus interface with my Spartan 3E to tap the bus traffic coming from keypresses. I'm using the LCLK from the bus and the FPGA 50Mhz clock for my...
 
JTAG IR length detection
We are currently building a board at work that will have connectors for X number of boards (that is between 0 and the number of connectors on the board) which will have FPGAs on them. We are looking...
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How can I create a direct FSL connection?
Hi all ... I'm new to using Xilinx's EDK (version 10.1.02) and could use a little help. I'd like to create a direct FSL connection between a MicroBlaze processor and a peripheral. I generated the...
 
EBAY: XC2V1000-5FG456C
FYI: -Martin
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2 BUFIOs in the same clock-capable pair?
I have 2 clock inputs coming into the FPGA through a clock-capable IO pair (AN19 and AN20). The clock inputs are of the same frequency, but not in phase. Is it possible to route each through their own...
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How do I send data and receive data from the FPGA and simulink/matlab
Hi all, I am using Altera DSP Builder to implement an OFDM receiver. I am working on Stratix II Altera FPGA.I need to send data into the DAC (in the FPGA board) from the matlab worspace and loop it to...
 
How to download bitstream into Cyclone III starter board
Hi All, I am migrating from Spartan 3e to Cyclone III. We bought only cyclone II starter board. We don't have any USB blaster download cable. I devlope the my current design. Now i want to download...
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Spartan 3E I/O Pins -- LPC Bus Interface
Im trying to make a LPC bus interface to record the bus traffic as a result of keypresses. Im using the clk from the LPC bus as my process clock. But it seems that the LFRAME# signal is always high...
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Altera FPGA and data from matlab workspace.
Hey, I need to send some data to the Altera Stratix II FPGA board from the matlab workspace and then do some FFT, FIR process on that and then return the data from the FPGA back into the matlab...
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What's wrong with this Virtex4 DCM?
I'm using the DCM instantiation reported below, on a Virtex4fx60 target. I have two different boards (ICS-8550) the differ only for the ruggedization level, the boards are almost the same and so...
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SBC with ADC, 1GE, and SATA2?
I'm lokking for a small (4x6", 6x8", range) SBC that has a reasonably good A/D converter (100+MSPS), at least one 1G ethernet, and one or more SATA-2 ports. I'm not picky about the processor. Anything...
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