Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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protocol layer
please tell me if any one know or have core of PL (protocol layer) in usb core. please tell me if any one know about PL (protocol layer)functionality and timing diagram in usb core free of bugs. If...
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15 years ago
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full timing diagram
Please tell any link from i would easily download full timing diagram of all internal block diagrams of usb core. Please give me if any one have full timing diagram of all internal block diagrams of...
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15 years ago
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free of bugs
Please tell me any link from i would easily download usb core which will be free of bugs.
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15 years ago
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Read files from Compact Flash
Hi all, I'm working on a dynamically reconfigurable project on ML402 (virtex-4 sx35) and, for this, I have to load partial bitstreams from a Compact Flash. I successfully generated a file that works...
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15 years ago
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XAPP240 - Design Files
Hi newsgroup, does someone know whether there are design files available for Xilinx application note "XAPP240 - High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices" ? I did not found...
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15 years ago
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usb core block diagram
I am mudassir. I want to get internal block diagram of usb core 2.0 or any other. Please give me if any one have this internal block diagram with full signals and timing diagram so that i can easily...
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15 years ago
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defunct Platform USB cable
Yesterday, one of my Platform USB cables ceased working. I opened the box and found cold solder joints at the USB connector. Since 1.) the connector pads are in the shadow of the shield, they probably...
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15 years ago
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FPL 2008 : Call for Participation
FPL International Conference on Field Programmable Logic and Applications Call for Participation The early registration deadline is August 1st For more details about registration and traveling...
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15 years ago
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Xilinx Spartan-3E Microblaze Program Execution
Hello all, I am a beginner with the Xilinx EDK and Platform Studio software for programming a Microblaze processor. I have googled several EDK tutorials, but few have met my platform specifications...
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15 years ago
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Xilinx/Altera gate equivalence
Are there any rules of thumb to figure out the equivalent number of logic resources needed to implement the same design on Stratix IV vs., say, Virtex-4/5? I am thinking of random logic, i.e. a CLB...
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15 years ago
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AURORA streaming
Target FPGA: Virtex II PRO I generated 2 designs including 4 AURORA single lane CORE each, configured in streaming : The first 4 are on bottom edge in the first design and the others are on TOP edge...
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15 years ago
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No open-drain in V5 to drive an external LED?
HI, on our PCB there is a LED directly connected to a Virtex5 I/O pad. The LED is connected through a series resistor to 3.3 V. As it seems Virtex devices do not support open-drain outputs. If I drive...
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15 years ago
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unified protocol
Hai, Any anyone can list test cases to verify unified protocol. regards, raj
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15 years ago
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Xilinx Virtex 4
I need help with immediate delivery of two Virtex 4 FPGA's. The part numbers are XC4VLX80-11FFG1148C (50pcs) and XC4VLX25-11FFG668C (25pcs). Anything that you can do is appreciated. Regards, Jon E....
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15 years ago
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Fifo Simulation Error
I've initiated the component and the instance according to the .vho files created along when I created my FIFO with the core generator. I've copied all the files into the same directories, but i just...
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15 years ago
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