1. Home
  2. Field-Programmable Gate Arrays
  3. 8B/10B Xilinx Paper

8B/10B Xilinx Paper

Hello newsgroup,

I am trying to understand the Xilinx reference design (XAPP391: Design of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD)). When performing the functional simulation (which is included in the download files) the error detection signal of the decoder becomes active on decoding of 10bit words 0x1C7, 0x1BE, 0x13E, 0x0BE and 0x2BE.

The testbench provided with the design connects the encoder and the decoder, so that only legal 10bit words get into the decoder.

8bit --> enc --> 10bit --> dec --> 8bit

So why does these errors occur ? Has someone already used that reference design and has met difficulties in simulation or real hardware implementation ?

Thank you. Best regards Andre

Reply to
ALuPin
Loading thread data ...

Is it possible that there is error verification conditions in the testbench, ie. the errors are injected on purpose to see if error checking works?

Reply to
mk

I think that there is no error injection in the testbench. In the error cases the 8bit words presented by the decoder are OK.

Reply to
ALuPin

When changing the order of 8bit words (integer) into the encoder from a)...236 - 237 - 238 - 239... to b)...236 - 8 - 238 ... (encoded word of 8 has negative disparity)

the error detection module does not show an error for the 0x1C7 (encoded word of 238).

The question is how to find the error in the encoder description ...

Rgds Andre

Reply to
ALuPin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.