Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Regarding process time calculation
Sir I want to know that how we can calculate time taken by a process or in Xilinx ISE anywhwhere we can see it as we are using concurrent programming and want to know time taken by each process in...
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12 years ago
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Re: FPGA security, Actel down, now Xilinx too?
The paper implies the cost is minimal, at least for the V2P parts. It seems that the equipment required places the attack within the reach of many universities and electronics companies. "A full key...
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12 years ago
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Pipeline stages of the Multiplier core (ISE Coregen)
Hello friends I can't understand how the Pipeline stages affect the multiplier core? I tested 1 stage and 4 stages. The result is given with 1 clock for 1 stage, and 4 clocks for 4 stages. When i...
1
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12 years ago
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die's in different packages
can someone tell me if there is any differences in the die for the following 2 devices in virtex-7 XC7VX415TFFG1158 and XC7VX415TFFG1927 Both these devices are listed as having same logic resources....
6
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12 years ago
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6 | |
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DVI-decoder clock question
Let say I have two DVI streams - generated by two encoders, those have different video contents but same pixel clock The two tmds streams travel thru cables then - are decoded by two decoders - then...
3
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12 years ago
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Bitstream compression
Hey all-- So my experience with the native bitstream compression algorithms provided by the FPGA vendors has been that they don't actually achieve all that much compression. This makes sense given...
15
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12 years ago
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image storing into BRAM
dear all, i want to store image from PC to BRAM of an FPGA.i have image 192x96 size. 1) which type of interfacing should i use to transfer image into BRAM from PC 2) how to write a program for it? do...
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12 years ago
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VHDL horror in Xcell 76
There is an utterly horrible VHDL howler on page of 45 of the latest Xcell Journal. Two example codes for a register with reset are given: signal Q: std_logic:=?1?; ... async: process (CLK,RST) begin...
7
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12 years ago
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Question on PCI-express verssus Standard PCI performance
Hi everyone, I'm working on a conversion project where we needed to convert a PCI acquisition card to a PCI-express (x1) acquisition card. The project is essentially the same except instead that the...
6
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12 years ago
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6 | |
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synthesizing
Hi all I want to calculate a simple formula, including multiply and division operands. I use Verilog language to program FPGA. Can I use the sign of Multiplication (*) and Division (/)? Or I have to...
3
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12 years ago
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About the setup time of BUFGMUX in Spartan6
I'm so confused about the setup time of BUFGMUX. In the datasheet of Spartan6, this spec is defined relatively to rising edge. But if the structure of BUFGMUX is like Then the setup time should be...
1
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12 years ago
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Post-map simulation: timing violation and delays
Hi all, I am trying to implement a custom counter (with clock and enable inputs); synthesis and behavioral & post-translate simulation pass just fine (using ISE WebPack 13.2). On post-map simulation,...
6
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12 years ago
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6 | |
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source synchronous DDR bus with non-continuous clock
I'm hoping to get some help/advise on how to design this interface. We're targeting Spartan-6. There=92s a bidirectional, source synchronous, DDR, single-ended bus running at only 25Mhz. The problem...
8
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12 years ago
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Speed attained by virtex 6
Dear sir, I am working on the virtex 6, XC6VLX550T FF1759 speed grade -1 , using finite state machines with high operands, (113 bits), in Galois field inverse theory. The problem I face is that I got...
2
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12 years ago
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sdxc
Anyone familiar with SDXC host controller? I'm not getting the performance I need because I am getting too much delay between writes using CMD25. I'm trying to stream video, do I have to use CMD20 or...
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12 years ago
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