8051 IP core

CODE_IS_BAD schrieb:

If this code is for free, download it, look at it, you will figure out easily, if it can be used or not. Anyway in that area you should at least understand what the code is doing ... ;-)

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Its VHDL so why couldnt it be? Since it appears to be LGPL'd, just download it and try.. what do you have to lose?

Why don't you take a look at the following 8051 from Hitech Global:

Their core is proven in multiple ASICs and FPGAs

Funny nobody mentioned Nexar : the 8051 core comes with the package, + development & debugging tools. Other cores provided are 16c5x, Z80, a small RISC ... otomh It's quite easy to set up and use in an FPGA context indeed.

Bert Cuzeau

Hi all... thanx for the answers.... what i am looking for is a free IP core.... And if i see the oregano's core it does not provide for SFR address and data bus.... Is there any free IP core that provides that and if not then some tips on how to modify the core to add SFR busses ??? thanx in advance........

Hi,

I am using Oregano's mc8051 IP Core on a Altera Cyclone II FPGA (EP2C35) Board with great success. I have synthesized this core many times with Quartus (several procets). The occupied area is about 12%, fmax is about 20 MHz.

For my own interest I've tried fitting the core to a Xylinx device, an XC3S200-PQ208 and it won't fit:

Number of Slice Flip Flops: 566 out of 3,840 14% Number of 4 input LUTs: 4,562 out of 3,840 118% (OVERMAPPED) Logic Distribution: Number of occupied Slices: 2,356 out of 1,920

122% (OVERMAPPED) Number of Slices containing only related logic: 2,284 out of 2,356 96% Number of Slices containing unrelated logic: 72 out of 2,356 3% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 4,669 out of 3,840 121% (OVERMAPPED) Number used as logic: 4,562 Number used as a route-thru: 107 Number of bonded IOBs: 156 out of 141 110% (OVERMAPPED) IOB Flip Flops: 47 Number of MULT18X18s: 1 out of 12 8% Number of GCLKs: 1 out of 8 12%

It may be ISE but I can't seem to make a symbol either? It comes up with an internal error!:

FATAL_ERROR:HDLParsers:vhptype.c:172:$Id: vhptype.c,v 1.6 2001/10/12

21:32:28 weilin Exp $:200 - INTERNAL ERROR... while parsing c:/temp/8051/mc8051_core_.vhd line 222. Contact your hot line. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at If you need further assistance, please open a Webcase by clicking on the "WebCase" link at

There aren't 222 lines in "mc8051_core_.vhd"!

It's not ISE, it's your selection of a Spartan-III part. You can't compare a EP2C35 device (33,216 LUTs/475 IOs) to a 3S200-PQ208 (3,840 LUTs/141 IOS). The part that you selected was 10% the size of the other part!!!

The OP said the EP2C35 was about 12% used which is about 4K LUTs. This isn't too far off from your report.

Select a larger Spartan-III part with more IOs (at least 156 per your report) and it should go through without a problem.

Ed

Hi,

Oregano's core does not support an SFR bus. It's not a problem to add this feature as long as you don't need bitadressable SFRs. => So it's better to add your own SFRs to control_mem and connect them to your custom units (as it is done with the mc8051 peripherals) I have done this to upgrade the mc8051 core to an 8052 (added Timer 2).

They are also a bit more expensive then free. I think the parent poster was looking for a freeIP ..

Many thanks. I was a bit disappointed that I couldn't create a symbol and then leave off the bits I didn't want such as serial comms etc. Otherwise I accept your points, just that it makes for an expensive processor.

HI Friend... thanx for the replies... Plese tell me what all files need to be modified. Control_mem is for sure. and also will we have to modily control_asm also ??? Please elaborate .... Some more help is highly appreciated... thanx again...

Hi,

do you mean control_fsm (not control_asm) ? But no. When you want to add some FSRs you only have to change "control_mem_rtl.vhd"

control_fsm is the controlling FSM (core-control) which controls the opcode execution process. You only have to modify this file when you want to change the behaviour of some instructions. => There are already two small bugs at the latest version provided by Oregano (CJNE Ri,# Instruction does not update Carry, RETI Intruction does not work correctly at some cases) I can send you an fixed version of control_fsm if you want.

hi AVG.... yep .. i will be delighted if u can send me the fixed one (the one that has the SFR expansion capabilities also). Do u need my email ID or u can get that from this site itself?? Once again Thanx a lot..........

I will send the modified vhdl-files to snipped-for-privacy@gmail.com Is this ok ?

Thats right.........Thank u.....