80000 Bit Shift Register

I am implementing an 80000 Element Shift register to be used as a very long (1Sec) digital delay generator. (Yes, its that big). It is clocked at 80kHz.

Its a very simple design, just an ordinary shifter register with 80k elements. It is being implemented in a V2Pro (Digilent XUP Board).

I have simulated the design and it works OK. I am now trying to synthesize the design and it is taking a *VERY* long time. I tried to synthesize on my PC (P4 3.2GHz, 1G Ram) when I left work last night. It failed 5 hours later with an out of memory error. I am now trying on a Xeon Work station with 3GB of RAM.

Any pointers on how to make this synthesize faster?

What kind of machines are people using out there to synthesize large designs?

Reply to
Eli Hughes
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Here is my Code:

module shift(Clk, SIn, SOut); input Clk; input SIn; output SOut;

reg [80000:0] MyShift; reg Out;

initial begin MyShift = 0; Out=0; end

assign SOut = Out;

always @(posedge Clk) begin MyShift

Reply to
Eli Hughes

At 80 kHz, it would be easy to make a shift register out of the BRAMs if you aren't interested in the intermediate results. i.e. a FIFO. Each BRAM has

18kbits. Search the Xilinx website for FIFO to see how to implement this. HTH, Syms.
Reply to
Symon

What about using block ram and just an index pointer? Shift-in: set current bit at index, increment index pointer, read current bit and shift it out. If the index pointer reaches some limit, reset it to 0. If you clock the FPGA with a higher frequency, then the read/write cycles are no problem with your shift clock.

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Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

I don't know much about Verilog, but if you can use an index into the MyShift register instead of actually shifting it, maybe your synthesize program can infer a block ram automaticly.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

At 80kHz you could probably get a 17-bit binary counter running. If not you can use linear feedback shift register.

Petter

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Reply to
Petter Gustad

I would use block RAM resources for the delay-line storage instead of FFs. That way you just need 5 RAM blocks per data bit, and a counter or two, rather than creating some massive power-hungry flip-flop spaghetti... :)

-Ben-

Reply to
Ben Jones

snipped-for-privacy@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de

In the past, I had problems trying to get synthesis to build a memory of std_logic types (i.e. a long std_logic_vector). To get around it I declared an array of one bit std_logic_vectors, and that worked fine.

You might be able to declare an array of 80000 of those, and then use a binary counter to read/write the memory. I've had synthesis tools stitch together multiple ram primitives automatically in the past (in depth and in width), but not that deep with block rams (never tried it).

Sorry, my expertise is in vhdl, not verilog, but maybe you get the idea anyway.

Andy

Reply to
Andy

haven't checked if it actually works but it should be close, synthesize in seconds infering 5 blockrams:

module shift(clk,in,out);

input clk,in; output out;

reg out;

reg [80000:0] shiftreg; reg [16:0] index;

always@(posedge clk) begin out

Reply to
langwadt

I just tried Precision on your code and it took 10 minutes to synthesize on an AMD3500+ with 4Gbyte of memory. Compile took 400Mbyte, and synthesis

1.4Gbyte (rough estimate from the task manager on Win2K).

Hans

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Reply to
HT-Lab

Thanks for all of the pointers. I ended up just implementing the delay with BlockRam. The simulation worked great. I will post the code as soon as I very *real* operation.

HT-Lab wrote:

Reply to
Eli Hughes

Here is working (Actually Implement in Silicon) code:

module Delay(Clk, DataIn, DataOut);

input Clk; input DataIn; output DataOut;

reg BitRAM [0:950000]; reg ShiftOutput;

reg [24:0] InAddress; reg [24:0] OutAddress;

reg [9:0] ClkDiv; reg LocalClk;

reg Cycle;

always @(posedge Clk) begin

ClkDiv

Reply to
Eli Hughes

Any comments on relative Simulate and P&R times, for others that may follow ?

-jg

Reply to
Jim Granville

And here is one, more in the original flavor, that uses inferred shift registers and a little hierarchy to split things up for physical synthesis.

alan

module shift(Clk, SIn, SOut); input Clk; input SIn; output SOut; parameter width = 1024 ; reg [width-1:0] MyShift;

assign SOut = MyShift[width-1];

always @(posedge Clk) begin MyShift

Reply to
ajjc

Forgot to mention that the design is now 950000 element shift register. This code snippet was written for the Digilent XUP board.

I did not measure the simulation time in any precise way but it was only a few seconds between starting the simulation (ISE simulator) and getting my results. My test bench was simple, clocked in a somewhat random pulse train at starting time 0 and ran the simulation to about

1000000 clock cycles later. The pulse train was delayed as expected.....

The total time to Synthesize to generating a bit stream was about 1 minute on a P4 2.4GHZ with 1GB RAM.

The bitram implementation is very quick to synthesize and P&R. The code could be cleaned up a bit, but it functions well for its intended purpose ...... i.e. a colleague stops in my office and tells me to build a 1 sec delay generator with 1uS resolution. I can't spend any money on parts and it needs done by the next morning with some BNC connectors hanging from the board.

Reply to
Eli Hughes

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