Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Reference books on microprocessor design with VHDL
Hello, i follow the book Microprocessor design with VHDL by Enoch O.Hwang. I want some reference books and some web address on this topic.
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12 years ago
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ADC by using counter method on FPGA using VHDL language
Hello,i have some idea about vhdl.I want coding of ADC by using counter method on FPGA by using VHDL.. I know the some idea about this program the following process. a) first reset the counter b)the...
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12 years ago
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microprocessor design with vhdl
Hello,i have knowledge of basic vhdl and i have implement a few fundemental programs on digital circuits. Iam very new to FPGA.I want to experiment a complete details of microprocessor design with...
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12 years ago
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Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
Co-sponsored by IEEE NCA Consultants Network, Baltimore Consultants Network, Society on Social Implications of Technology, Baltimore and NoVA/Wash. Computer Society, and Region 2 PACE Committee...
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12 years ago
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FPGA development
Hello I am very new to FPGA's (background being ASIC design). I would like to map some designs onto FPGA's as a starting point. I want to experiment with the complete FPGA flow, starting with writing...
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12 years ago
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Peter Alfke has passed away
Those who've been on this newsgroup for any period of time will remember Peter Alfke, the Xilinx legend, and his infectious enthusiasm. He was a great help as I got into FPGA design 8 years ago, as I...
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12 years ago
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USB hangs on the Xilinx USB II Cable
The Xilinx USB II cable hangs on a regular basis. I've found that pulling the USB connector out and putting it back in isn't sufficient, the only way that I can get Chipscope to see it again is to...
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12 years ago
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Altera FPGA weirdness
Hi, We have a new board we just designed, and we're trying to fire up the first one. It has an Altera EP2AGX45DF29C5N on board; says so right on the label. When we hook up the JTAG USB Blaster pod and...
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12 years ago
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Synapticad BugHunter and VeriloggerExtreme
Greetings: They gave me a 6-mo eval license for those, which I will begin tinkering with in upcoming weeks. I have so far used only Icarus Verilog for sims, ever since Modelsim stopped being included...
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12 years ago
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Doulos training courses at Xilinx
Hi: While I'm very able to learn on my own, I feel that at my age and with so many people pulling at me every minute, that to assemble the hours of focussed attention to actually work through a...
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12 years ago
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Spartan changes in glitch sensitivity
Hello, all, I know this refers to graveyard parts, but we have reason to keep using them. Anyway, I made a new batch of motherboards that use a 5 V Spartan as the slot select control logic. I have...
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12 years ago
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Microblaze Resources such as BRAMS, LUTS
Hello all, I am a newbie in the FPGA stuff!.. I wanted to know some FPGA resource consumption by the microblaze but could not find some specific details such as how much BRAMS does it take (with...
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12 years ago
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high speed place and route about xilinx
Now I am troubled that I must wait several hours to compile large circuits,and the place and route result is different from each time,for example the p&r time for this time is may be 2hrs and may be 5...
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12 years ago
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Is it possible to use a remote desktop viewer on NIOS Linux
Hello , I am having a project where I need to take control of a pc or a smart phone which has a VNC server using FPGA so I need to run a client from the FPGA side . Is this possible ? My kit is the...
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12 years ago
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Xilinx EDK: XPS netlist combination error
Hello all, Does anyone know why I keep getting errors like this: " ERROR:EDK:708 - Can not get list of netlist files for core xps_fb_img_xform 1.01.a . The pcore has a pre-synthesized netlist...
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12 years ago
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